CY7C1360B CYPRESS [Cypress Semiconductor], CY7C1360B Datasheet - Page 27

• Manufacturer Part Number: CY7C1360B
• Description: 9-Mbit (256K x 36/512K x 18) Pipelined SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05291 Rev. *C
Switching Waveforms
Write Cycle Timing
Note:
23. Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW
Data Out (Q)
Data In (D)
ADDRESS
ADSC
ADSP
BWE,
ADV
BW
CLK
GW
OE
CE
X
BURST READ
High-Z
t ADS
[22, 23]
t CES
t AS
A1
t ADH
t CEH
t AH
t CH
t
OEHZ
Byte write signals are
ignored for first cycle when
ADSP initiates burst
t CYC
(continued)
t ADS
t CL
t DS
Single WRITE
D(A1)
t ADH
t DH
A2
D(A2)
DON’T CARE
t WES
D(A2 + 1)
BURST WRITE
t WEH
UNDEFINED
D(A2 + 1)
X
ADV suspends burst
LOW.
D(A2 + 2)
ADSC extends burst
D(A2 + 3)
t ADS
A3
D(A3)
t ADH
t
ADVS
t WES
CY7C1360B
CY7C1362B
Extended BURST WRITE
D(A3 + 1)
t
t WEH
ADVH
Page 27 of 34
D(A3 + 2)