AD9500TE AD [Analog Devices], AD9500TE Datasheet - Page 3

• Manufacturer Part Number: AD9500TE
• Description: Digitally Programmable Delay Generator
• Manufacturer: AD [Analog Devices]

Parameter
SUPPORT FUNCTIONS
DIGITAL OUTPUTS
POWER SUPPLY
NOTES
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Specifications subject to change without notice.
EXPLANATION OF TEST LEVELS
Test Level
I
II – 100% production tested at +25 C, and sample tested at
III – Periodically sample tested.
IV – Parameter is guaranteed by design and characterization
V – Parameter is a typical value only.
VI – All devices are 100% production tested at +25 C. 100%
REV. D
Absolute maximum ratings are limiting values, to be applied individually, and beyond which serviceability of the circuit may be impaired. Functional operability under
Typical thermal impedance
R
The digital data inputs must remain stable for the specified time prior to the LATCH ENABLE signal.
The digital data inputs must remain stable for the specified time after the LATCH ENABLE signal.
The TRIGGER and RESET inputs are differential and must be driven relative to one another. Both of these inputs are ECL compatible, but can also be used with
Outputs terminated through 50
Program Delay = 0.0 ps (Digital Data = 00
Change in total delay through AD9500, exclusive of changes in minimum propagation delay t
any of these conditions is not necessarily implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
TTL logic families in a limited fashion.
Measured from the 50% transition point of the reset signal input, to the 50% transition point of the resetting output.
Minimum time from falling edge of RESET to triggering input, to ensure a valid output event.
Minimum time from triggering event to rising edge of RESET, to ensure a valid output event.
Measured from the LATCH ENABLE input to the point when the AD9500 becomes 8-bit accurate again, after a full-scale change in the programmed delay.
Standard 10K and 10KH ECL families operate with a 1.1 mV/ C drift by design.
Supply voltages should remain stable within 5% for normal operation.
Measured at 5% of –V
SET
ECL
ECL
Offset Adjust Range
Logic “1” Voltage
Logic “0” Voltage
Positive Supply Current (+5.0 V)
Negative Supply Current (–5.2 V)
Nominal Power Dissipation
Power Supply Rejection Ratio
– 100% production tested.
Full-Scale Range Sensitivity
Minimum Propagation Delay
= 10 k (Full-scale delay = 100 ns).
24-Lead Cerdip
28-Leadless PLCC (Plastic)
28-Leaded Ceramic LCC
Sensitivity
specified temperatures.
testing.
production tested at temperature extremes for extended
temperature devices; sample tested at temperature ex-
tremes for commercial/industrial devices.
REF
REF
Voltage Drift
15
S
and +V
7
14
S
resistors to –2.0 V.
.
16
θ
θ
θ
JA
JA
JA
H
= 56 C/W; θ
= 60 C/W; θ
= 69 C/W; θ
). In Operation, any programmed delays are in addition to the Minimum Propagation Delay.
Test
Level
IV
V
V
VI
VI
I
VI
I
VI
V
I
I
JC
JC
JC
= 16 C/W
= 22 C/W
= 25 C/W
Temp
+25 C
Full
Full
+25 C
Full
+25 C
Full
+25 C
+25 C
+25 C
Full
Full
–3–
Min
–1.4
–1.1
Model
AD9500BP –25 C to +85 C
AD9500BQ –25 C to +85 C
AD9500TE –55 C to +125 C 28-Leaded LCC,
AD9500TQ –55 C to +125 C 24-Lead Cerdip,
AD9500BP/BQ
–25 C to +85 C
PD
Typ
–1.3
1.1
–2
24
37
312
70
150
.
Temperature
Ranges
Max
–1.2
28
30
42
44
300
500
–1.5
ORDERING GUIDE
Min
–1.4
–1.1
Package
Descriptions
28-Leadless PLCC (Plastic),
Industrial Temperature
24-Lead Cerdip,
Industrial Temperature
Extended Temperature
Extended Temperature
–55 C to +125 C
AD9500TE/TQ
Typ
–1.3
1.1
–2
24
37
312
70
150
Max
–1.2
–1.5
28
30
42
44
300
500
AD9500
Package
Options
P-28A
Q-24
E-28A
Q-24
Units
V
mV/ C
mA
V
V
mA
mA
mA
mA
mW
ps/V
ps/V