AD9511BCPZ-REEL AD [Analog Devices], AD9511BCPZ-REEL Datasheet - Page 44

• Manufacturer Part Number: AD9511BCPZ-REEL
• Description: 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs
• Manufacturer: AD [Analog Devices]

AD9511
Table 22. Serial Control Port Timing
Parameter
t
t
t
t
t
t
t
DS
DH
CLK
S
H
HI
LO
SCLK
SDIO
CSB
SCLK
SDIO
CSB
t
Description
Setup time between data and rising edge of SCLK
Hold time between data and rising edge of SCLK
Period of the clock
Setup time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
TIMING DIAGRAM FOR TWO SUCCESSIVE COMMUNICATION CYCLES. NOTE THAT CSB MUST
BE TOGGLED HIGH AND THEN LOW AT THE COMPLETION OF A COMMUNICATION CYCLE.
t
DS
S
16 INSTRUCTION BITS + 8 DATA BITS
COMMUNICATION CYCLE 1
BI N
t
HI
t
DH
Figure 52. Use of CSB to Define Communications Cycles
Figure 51. Serial Control Port Timing—Write
t
CLK
CSB TOGGLE INDICATES
Rev. A | Page 44 of 60
t
LO
CYCLE COMPLETE
BI N + 1
16 INSTRUCTION BITS + 8 DATA BITS
t
PWH
COMMUNICATION CYCLE 2
t
H