AD9511BCPZ-REEL AD [Analog Devices], AD9511BCPZ-REEL Datasheet - Page 46

• Manufacturer Part Number: AD9511BCPZ-REEL
• Description: 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs
• Manufacturer: AD [Analog Devices]

AD9511
Addr
(Hex)
3D
3E
3F
40
41
42,
43,
44
45
46,
47,
48, 49
4A
4B
4C
4D
4E
4F
50
51
52
53
54,
55,
56,
57
58
59
5A
Parameter
OUTPUTS
LVPECL OUT0
LVPECL OUT1
LVPECL OUT2
LVDS_CMOS
OUT 3
LVDS_CMOS
OUT 4
CLK1 AND
CLK2
Clocks Select,
Power-Down
(PD) Options
DIVIDERS
Divider 0
Divider 0
Divider 1
Divider 1
Divider 2
Divider 2
Divider 3
Divider 3
Divider 4
Divider 4
FUNCTION
FUNCTION
Pin and Sync
Update
Registers
END
Bit 7 (MSB)
Bypass
Bypass
Bypass
Bypass
Bypass
Used
Not
Not Used
Not Used
Not Used
Low Cycles <7:4>
Low Cycles <7:4>
Low Cycles <7:4>
Low Cycles <7:4>
Low Cycles <7:4>
Bit 6
Set FUNCTION Pin
Sync
Sync
Sync
Sync
Sync
No
No
No
No
No
Not Used
Not Used
Not Used
Bit 5
CLKs in
Force
Force
Force
Force
Force
PD
Not Used
Rev. A | Page 46 of 60
Bit 4
Driver On
REFIN PD
Driver On
Start H/L
Start H/L
Start H/L
Start H/L
Start H/L
Inverted
Inverted
PD Sync
CMOS
CMOS
Not Used
Not Used
Not Used
Not Used
Bit 3
Select
Select
PD All
Logic
Logic
CLK
PLL
Ref
PD
to
Output Level
Output Level
Output Level
<3:2>
<3:2>
<3:2>
Bit 2
CLK2
Phase Offset <3:0>
Phase Offset <3:0>
Phase Offset <3:0>
Phase Offset <3:0>
Phase Offset <3:0>
Sync
High Cycles <3:0>
High Cycles <3:0>
High Cycles <3:0>
High Cycles <3:0>
High Cycles <3:0>
Reg
PD
Output Level
Output Level
<2:1>
<2:1>
Bit 1
Power-Down <1:0>
Power-Down <1:0>
Power-Down <1:0>
Select
CLK1
Sync
PD
Bit 0
(LSB)
Registers
Update
Output
Output
Enable
CLK IN
Power
Power
Select
Sync
Def.
Value
(Hex)
08
08
08
02
02
01
00
00
11
00
33
00
00
00
11
00
00
00
Notes
ON
ON
ON
LVDS, ON
LVDS, ON
Input
Receivers
All Clocks
ON, Select
CLK1
Divide by 2
Phase = 0
Divide by 4
Phase = 0
Divide by 8
Phase = 0
Divide by 2
Phase = 0
Divide by 4
Phase = 0
FUNCTION
Pin =
RESETB
Self-
Clearing
Bit