AD9516-0_07 AD [Analog Devices], AD9516-0_07 Datasheet - Page 78

• Manufacturer Part Number: AD9516-0_07
• Description: 14-Output Clock Generator with Integrated 2.8 GHz VCO
• Manufacturer: AD [Analog Devices]

AD9516-0
Table 60. System
Reg.
Addr
(Hex) Bit(s) Name
230
230
230
Table 61. Update All Registers
Reg.
Addr
(Hex) Bit(s) Name
232
<0>
<2>
<1>
<0>
Update All
Registers
Power-Down Sync
Power-Down Distribution Reference
Soft SYNC
This bit must be set to 1 to transfer the contents of the buffer registers into the active registers. This happens
on the next SCLK rising edge. This bit is self-clearing; that is, it does not have to be set back to 0.
<0> = 1 (self-clearing); update all active registers to the contents of the buffer registers.
Description
Description
Power down the SYNC function.
<2> = 0; normal operation of the SYNC function.
<2> = 1; power-down sync circuitry.
Power down the reference for distribution section.
<1> = 0; normal operation of the reference for the distribution section.
<1> = 1; power down the reference for the distribution section.
The soft SYNC bit works the same as the SYNC pin, except that the polarity of this bit
reversed. That is, a high level forces selected channels into a predetermined static
state, and a 1-to-0 transition triggers a sync.
<0> = 0; same as SYNC high.
<0> = 1; same as SYNC low.
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