AD9518-4A-PCBZ AD [Analog Devices], AD9518-4A-PCBZ Datasheet - Page 36

• Manufacturer Part Number: AD9518-4A-PCBZ
• Description: 6-Output Clock Generator with Integrated 1.6 GHz VCO
• Manufacturer: AD [Analog Devices]

AD9518-4
The duty cycle at the output of the channel divider for various
configurations is shown in Table 33 to Table 35.
Table 33. Duty Cycle with VCO Divider, Input Duty Cycle Is 50%
VCO
Divider
Even
Odd = 3
Odd = 5
Even, Odd
Even, Odd
Table 34. Duty Cycle with VCO Divider, Input Duty Cycle Is X%
VCO
Divider
Even
Odd = 3
Odd = 5
Even
Odd = 3
Odd = 3
Odd = 5
Odd = 5
Table 35. Channel Divider Output Duty Cycle When the
VCO Divider Is Not Used
Input Clock
Duty Cycle
Any
Any
50%
X%
The internal VCO has a duty cycle of 50%. Therefore, when the
VCO is connected directly to the output, the duty cycle is 50%.
If the CLK input is routed directly to the output, the duty cycle of
the output is the same as the CLK input.
N + M + 2
1 (divider
bypassed)
1 (divider
bypassed)
1 (divider
bypassed)
Even
Odd
Even
Odd
Even
Odd
N + M + 2
1 (divider
bypassed)
1 (divider
bypassed)
1 (divider
bypassed)
Even
Odd
N + M + 2
1
Even
Odd
Odd
D
D
X
D
X
X
DCCOFF = 1
50%
33.3%
40%
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
DCCOFF = 1
50%
33.3%
40%
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
DCCOFF = 1
1 (divider
bypassed)
(N + 1)/
(M + N + 2)
(N + 1)/
(M + N + 2)
(N + 1)/
(M + N + 2)
Output Duty Cycle
Output Duty Cycle
Output Duty Cycle
DCCOFF = 0
50%
(1 + X%)/3
(2 + X%)/5
50%,
requires M = N
50%,
requires M = N + 1
50%,
requires M = N
(3N + 4 + X%)/(6N + 9),
requires M = N + 1
50%,
requires M = N
(5N + 7 + X%)/(10N + 15),
requires M = N + 1
DCCOFF = 0
50%
50%
50%
50%; requires M = N
50%; requires M = N + 1
DCCOFF = 0
Same as input
duty cycle
50%, requires M = N
50%, requires
M = N + 1
(N + 1 + X%)/(2 × N + 3),
requires M = N + 1
Rev. B | Page 36 of 64
Phase Offset or Coarse Time Delay (0, 1, and 2)
Each channel divider allows for a phase offset, or a coarse time
delay, to be programmed by setting register bits (see Table 36).
These settings determine the number of cycles (successive
rising edges) of the channel divider input frequency by which to
offset, or delay, the rising edge of the output of the divider. This
delay is with respect to a nondelayed output (that is, with a
phase offset of zero). The amount of the delay is set by five bits
loaded into the phase offset (PO) register plus the start high (SH)
bit for each channel divider. When the start high bit is set, the
delay is also affected by the number of low cycles (M) that are
programmed for the divider.
The sync function must be used to make phase offsets effective
(see the Synchronizing the Outputs—Sync Function section).
Table 36. Setting Phase Offset and Division for Divider 0,
Divider 1, and Divider 2
Divider
0
1
2
Let
Δt = delay (in seconds).
Δc = delay (in cycles of clock signal at input to D
T
(in seconds).
Φ =
16 × SH[4] + 8 × PO[3] + 4 × PO[2] + 2 × PO[1] + 1 × PO[0]
The channel divide-by is set as N = high cycles and M = low cycles.
Case 1
For Φ ≤ 15,
Δt = Φ × T
Δc = Δt/T
Case 2
For Φ ≥ 16,
Δt = (Φ − 16 + M + 1) × T
Δc = Δt/T
By giving each divider a different phase offset, output-to-output
delays can be set in increments of the channel divider input
clock cycle. Figure 40 shows the results of setting such a coarse
offset between outputs.
X
= period of the clock signal at the input of the divider, D
DIVIDER 0
DIVIDER 1
DIVIDER 2
DIVIDER INPUT
CHANNEL
X
X
Start
High (SH)
0x191[4]
0x194[4]
0x197[4]
X
SH = 0
PO = 0
SH = 0
PO = 1
SH = 0
PO = 2
= Φ
Figure 40. Effect of Coarse Phase Offset (or Delay)
0
1
Tx
2
Phase
Offset (PO)
0x191[3:0]
0x194[3:0]
0x197[3:0]
3
X
1 × Tx
2 × Tx
4
5
6
7
Low Cycles
M
0x190[7:4]
0x193[7:4]
0x196[7:4]
8
9 10 11 12 13 14 15
Data Sheet
X
).
High Cycles
N
0x190[3:0]
0x193[3:0]
0x196[3:0]
X