AD9518-4A-PCBZ AD [Analog Devices], AD9518-4A-PCBZ Datasheet - Page 43

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AD9518-4A-PCBZ

Manufacturer Part Number
AD9518-4A-PCBZ
Description
6-Output Clock Generator with Integrated 1.6 GHz VCO
Manufacturer
AD [Analog Devices]
Datasheet
Data Sheet
Table 40. Serial Control Port Timing
Parameter
t
t
t
t
t
t
t
t
DS
DH
CLK
S
C
HIGH
LOW
DV
SCLK
SDIO
CS
Description
Setup time between data and rising edge of SCLK
Hold time between data and rising edge of SCLK
Period of the clock
Setup time between CS falling edge and SCLK rising edge (start of communication cycle)
Setup time between SCLK rising edge and CS rising edge (end of communication cycle)
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
SCLK to valid SDIO and SDO (see Figure 49)
t
t
DS
S
BIT N
t
Figure 51. Serial Control Port Timing Diagram—Write
HIGH
t
DH
t
CLK
Rev. B | Page 43 of 64
t
LOW
BIT N + 1
t
C
AD9518-4

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