W83194R-39A WINBOND [Winbond], W83194R-39A Datasheet - Page 5

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W83194R-39A

Manufacturer Part Number
W83194R-39A
Description
100MHZ 3-DIMM CLOCK
Manufacturer
WINBOND [Winbond]
Datasheet
5.3 I
SDATA
SDCLK
5.4 Fixed Frequency Outputs
REF0 / PCI_STOP#
REF1 / *FS2
24MHz / *FS1
48MHz / *FS0
5.5 Power Pins
Vddq1
VddL1
VddL2
Vddq2
Vddq3
Vddq4
Vss
2
C Control Interface
SYMBOL
SYMBOL
SYMBOL
3,9,16,22,33,39,45 Circuit Ground.
PIN
PIN
19, 30, 36
23
24
46
25
26
2
6, 14
PIN
48
27
42
1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
- 5 -
Power supply for Ref [0:1] crystal and core logic.
Power supply for IOAPIC output, either 2.5V or 3.3V.
Power supply for CPUCLK[0:3], either 2.5V or 3.3V.
Power supply for PCICLK_F, PCICLK[0:4], 3.3V.
Power supply for SDRAM[0:12], and CPU PLL core,
nominal 3.3V.
Power for 24 & 48MHz output buffers and fixed PLL
core.
Serial data of I
pull-up resistor.
Serial clock of I
internal pull-up resistor.
14.318MHz reference clock. This REF output is the
stronger buffer for ISA bus loads.
Halt PCICLK(0:4) clocks at logic 0 level, when input
low (In mobile mode. MODE=0)
14.318MHz reference clock.
Latched input for FS2 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.
24MHz output clock.
Latched input for FS1 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.
48MHz output for USB during normal operation.
Latched input for FS0 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.
2
C 2-wire control interface with internal
2
C 2-wire control interface with
Publication Release Date: May 1998
FUNCTION
W83194R-39/-39A
FUNCTION
FUNCTION
PRELIMINARY
Revision 0.20

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