W83194R-630 WINBOND [Winbond], W83194R-630 Datasheet - Page 8

• Manufacturer Part Number: W83194R-630
• Description: 166MHZ CLOCK FOR SIS CHIPSET
• Manufacturer: WINBOND [Winbond]

8. FUNCTION DESCRIPTION
8.1 2-WIRE I2C CONTROL INTERFACE
The clock generator is a slave I2C component which can be read back the data stored in the latches
for verification. All proceeding bytes must be sent to change one of the control bytes. The 2-wire
control interface allows each clock output individually enabled or disabled.
W83194R-630A initializes with default register settings, and then itptional to use the 2-wire control
interface.
The SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high
during normal data transfer. There are only two exceptions. One is a high-to-low transition on SDATA
while SDCLK is high used to indicate the beginning of a data transfer cycle. The other is a low-to-
high transition on SDATA while SDCLK is high used to indicate the end of a data transfer cycle. Data
is always sent as complete 8-bit bytes followed by an acknowledge generated.
Byte writing starts with a start condition followed by 7-bit slave address [1101 0010], command code
checking [0000 0000], and byte count checking.
acknowledge (low) on the SDATA wire will be generated by the clock chip. Controller can start to
write to internal I
Bytes sequence order for I
Set R/W to 1 when read back the data sequence is as follows, [1101 0011] :
Clock Address
A(6:0) & R/W
Clock Address
A(6:0) & R/W
2
C registers after the string of data. The sequence order is as follows:
Ack
Ack
2
C controller :
8 bits dummy
Command code
Byte 0
Ack
Ack
- 8 -
8 bits dummy
Byte count
After successful reception of each byte, an
Byte 1
W83194R-630/-630A
Ack
Ack
Byte0,1,2...
until Stop
Byte2, 3, 4...
until Stop
On power up, the