CY7C1518AV18 CYPRESS [Cypress Semiconductor], CY7C1518AV18 Datasheet - Page 16

• Manufacturer Part Number: CY7C1518AV18
• Description: 72-Mbit DDR-II SRAM Two-Word Burst Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

Identification Register Definitions
Scan Register Sizes
Instruction Codes
Document Number: 001-06982 Rev. *I
Revision Number (31:29)
Cypress Device ID (28:12)
Cypress JEDEC ID (11:1)
ID Register Presence (0)
Instruction
Bypass
ID
Boundary Scan
EXTEST
IDCODE
SAMPLE Z
RESERVED
SAMPLE/PRELOAD
RESERVED
RESERVED
BYPASS
Instruction
Instruction Field
Register Name
Code
000
001
010
100
101
011
110
111
Captures the input and output ring contents.
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
Captures the input and output contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM output drivers to a high Z state.
Do Not Use: This instruction is reserved for future use.
Captures the input and output ring contents. Places the boundary scan register between TDI
and TDO. Does not affect the SRAM operation.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
11010100010010100
CY7C1518AV18
00000110100
000
1
Value
11010100010100100
CY7C1520AV18
00000110100
Description
000
1
Bit Size
109
32
3
1
Version number.
Defines the type of SRAM.
Allows unique identification of
SRAM vendor.
Indicates the presence of an ID
register.
CY7C1518AV18
CY7C1520AV18
Description
Page 16 of 29
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