CY7C1518AV18 CYPRESS [Cypress Semiconductor], CY7C1518AV18 Datasheet - Page 22

• Manufacturer Part Number: CY7C1518AV18
• Description: 72-Mbit DDR-II SRAM Two-Word Burst Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

Switching Characteristics
Over the Operating Range
Notes
Document Number: 001-06982 Rev. *I
Parameter
t
t
t
t
t
t
Setup Times
t
t
t
t
Hold Times
t
t
t
t
POWER
CYC
KH
KL
KHKH
KHCH
SA
SC
SCDDR
SD
HA
HC
HCDDR
HD
26. Unless otherwise noted, test conditions assume signal transition time of 2 V/ns, timing reference levels of 0.75 V, V
27. When a part with a maximum frequency above 167 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being
28. This part has an internal voltage regulator; t
Cypress
levels of 0.25 V to 1.25 V, and output loading of the specified I
operated and outputs data with the output timings of that frequency range.
t
t
t
t
t
t
t
t
t
t
t
t
t
Consortium
KHKH
KHKL
KLKH
KHKH
KHCH
AVKH
IVKH
IVKH
DVKH
KHAX
KHIX
KHIX
KHDX
Parameter
V
K clock and C clock cycle time
Input clock (K/K and C/C) HIGH
Input clock (K/K and C/C) LOW
K clock rise to K clock rise and C to
C Rise (rising edge to rising edge)
K/K clock rise t o C/C clock rise
(rising edge to rising edge)
Address setup to K clock rise
Control setup to K clock rise
(LD, R/W)
Double data rate control setup to
clock (K/K) Rise
(BWS
D
Address hold after K clock rise
Control hold after K clock rise
(LD, R/W)
Double data rate control hold after
clock (K/K) Rise
(BWS
D
DD
[26, 27]
[X:0]
[X:0]
(typical) to the first access
0
0
hold after clock (K/K) rise
setup to clock (K/K) Rise
, BWS
, BWS
Description
POWER
1
1
, BWS
, BWS
is the time that the power is supplied above V
2
2
, BWS
, BWS
OL
3
3
/ I
)
)
OH
[28]
and load capacitance shown in (a) of
1.32
1.32
1.49
Min Max Min Max Min Max Min Max Min Max
3.3
0.0
0.4
0.4
0.3
0.3
0.4
0.4
0.3
0.3
300 MHz
1
1.45
8.4
–
–
–
–
–
–
–
–
–
–
–
–
3.6
0.0
0.4
1.4
1.4
1.6
0.4
0.3
0.3
0.4
0.4
0.3
0.3
278 MHz
1
DD
min initially before a read or write operation can be initiated.
1.55
8.4
–
–
–
–
–
–
–
–
–
–
–
–
Figure 4 on page
0.35
0.35
0.35
0.35
4.0
1.6
1.6
1.8
0.0
0.5
0.5
0.5
0.5
250 MHz
1
REF
= 0.75 V, RQ = 250 , V
8.4
1.8
–
–
–
–
–
–
–
–
–
–
–
–
21.
5.0
2.0
2.0
2.2
0.0
0.6
0.6
0.4
0.4
0.6
0.6
0.4
0.4
200 MHz
1
CY7C1518AV18
CY7C1520AV18
8.4
2.2
–
–
–
–
–
–
–
–
–
–
–
–
DDQ
6.0
2.4
2.4
2.7
0.0
0.7
0.7
0.5
0.5
0.7
0.7
0.5
0.5
167 MHz
1
= 1.5 V, input pulse
Page 22 of 29
8.4
2.7
–
–
–
–
–
–
–
–
–
–
–
–
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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