ADF4150HVBCPZ AD [Analog Devices], ADF4150HVBCPZ Datasheet - Page 15

• Manufacturer Part Number: ADF4150HVBCPZ
• Description: High Voltage, Fractional-N
• Manufacturer: AD [Analog Devices]

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4
L2
0
0
1
1
M3
0
0
0
0
1
1
1
1
0
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
L1
0
1
0
1
M2
0
0
1
1
0
0
1
1
0
0
NOISE MODE
LOW NOISE MODE
RESERVED
RESERVED
LOW SPUR MODE
NOISE AND
LOW SPUR
M1
0
1
0
1
0
1
0
1
L2
0
MODES
LOW
OUTPUT
THREE-STATE OUTPUT
DV
GND
R COUNTER OUTPUT
N DIVIDER OUTPUT
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
RESERVED
L1
0
DD
M3
0
MUXOUT
M2
0
RESERVED
M1
0
RD2
0
1
R10
0
0
.
.
.
1
1
1
1
RD2
0
REFERENCE
DOUBLER
DISABLED
ENABLED
RD1
0
1
R9
RD1
0
0
1
1
1
1
.
.
.
0
REFERENCE DIVIDE-B Y-2
DISABLED
ENABLED
...
...
...
...
...
...
...
...
...
...
R10
0
R2
0
1
0
0
1
1
.
.
.
R9
0
R1
1
0
0
1
0
1
.
.
.
R8
C2
0
0
1
1
0
R COUNTER (R)
1
2
.
.
.
1020
1021
1022
1023
R7
C1
0
1
0
1
10-BIT R COUNTER
0
B1
0
1
R6
CLOCK DIVIDER MODE
CLOCK DIVIDER OFF
RESERVED
RESYNC ENABLE
RESERVED
Figure 22. Register 2 (R2)
Figure 23. Register 3 (R3)
B1
BOOST
ENABLE
DISABLED
ENABLED
Rev. 0 | Page 15 of 28
R5
0
R4
C2
MODE
CLK
DIV
D1
0
1
R3
DBR
CP3
0
0
0
0
1
1
1
1
C1
DOUBLE BUFFER
R4[DB22:DB20]
DISABLED
ENABLED
R2
D12
CP2
0
0
1
1
0
0
1
1
R1
D11
D1
CP1
0
1
0
1
0
1
0
1
D10
D12
0
0
0
0
.
.
.
1
1
1
1
0
I CP (µA)
5.1kΩ
48
96
144
192
240
288
336
384
D11
0
0
0
0
.
.
.
1
1
1
1
D9
12-BIT CLOCK DIVIDER VALUE
CP3
CURRENT
CHARGE
SETTING
...
...
...
...
...
...
...
...
...
...
...
...
D8
PUMP
CP2
U6
0
1
D2
0
0
1
1
.
.
.
0
0
1
1
DBR
D7
0
1
CP1
U5
0
1
LDF
FRAC-N
INT-N
D1
0
1
0
1
.
.
.
0
1
0
1
D6
RESERVED
BIT
RESERVED
NORMAL
OPERATION
U6
LDP
10ns
6ns
D5
CLOCK DIVIDER VALUE
0
1
2
3
.
.
.
4092
4093
4094
4095
U5
D4
1
D3
U3
U3
0
1
D2
U2
U2
0
1
ADF4150HV
POWER-DOWN
DISABLED
ENABLED
DB3
D1
U1
U1
0
1
CP
THREE-STATE
DISABLED
ENABLED
C3(0) C2(1) C1(1)
DB2
C3(0) C2(1) C1(0)
DB2
COUNTER
RESET
DISABLED
ENABLED
CONTROL
CONTROL
BITS
DB1
BITS
DB1
DB0
DB0