ADF4150HVBCPZ AD [Analog Devices], ADF4150HVBCPZ Datasheet - Page 18

• Manufacturer Part Number: ADF4150HVBCPZ
• Description: High Voltage, Fractional-N
• Manufacturer: AD [Analog Devices]

ADF4150HV
Reference Doubler
Setting the DB25 bit to 0 disables the doubler and feeds the
REF
1 multiplies the REF
it into the 10-bit R counter. When the doubler is disabled, the
REF
fractional synthesizer. When the doubler is enabled, both the
rising and falling edges of REF
PFD input.
When the doubler is enabled and the low spur mode is chosen,
the in-band phase noise performance is sensitive to the REF
cycle. The phase noise degradation can be as much as 5 dB for
REF
is insensitive to the REF
when the doubler is disabled.
The maximum allowable REF
enabled is 30 MHz.
RDIV2
Setting the DB24 bit to 1 inserts a divide-by-2 toggle flip-flop
between the R counter and the PFD. This function allows a 50%
duty cycle signal to appear at the PFD input, which is necessary
when the charge pump boost mode is enabled (see the Boost
Enable section).
10-Bit R Counter
The 10-bit R counter (Bits[DB23:DB14]) allows the input
reference frequency (REF
reference clock to the PFD. Division ratios from 1 to 1023 are
allowed.
Double Buffer
The DB13 bit enables or disables double buffering of
Bits[DB22:DB20] in Register 4. For information about how
double buffering works, see the Program Modes section.
Charge Pump Current Setting
Bits[DB11:DB9] set the charge pump current. This value
should be set to the charge pump current that the loop filter
is designed with (see Figure 22).
Lock Detect Function (LDF)
The DB8 bit configures the lock detect function (LDF). The LDF
controls the number of PFD cycles monitored by the lock detect
circuit to ascertain whether lock has been achieved. When DB8
is set to 0, the number of PFD cycles monitored is 40. When
DB8 is set to 1, the number of PFD cycles monitored is 5. It is
recommended that the DB8 bit be set to 0 for fractional-N mode
and 1 for integer-N mode.
IN
IN
IN
signal directly into the 10-bit R counter. Setting this bit to
falling edge is the active edge at the PFD input to the
duty cycles outside a 45% to 55% range. The phase noise
IN
frequency by a factor of 2 before feeding
IN
IN
duty cycle in the low noise mode and
) to be divided down to produce the
IN
IN
frequency when the doubler is
become active edges at the
IN
duty
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Lock Detect Precision (LDP)
The lock detect precision bit (Bit DB7) sets the comparison
window in the lock detect circuit. When DB7 is set to 0, the
comparison window is 10 ns; when DB7 is set to 1, the window
is 6 ns. The lock detect circuit goes high when n consecutive
PFD cycles are less than the comparison window value; n is set
by the LDF bit (DB8). For example, with DB8 = 0 and DB7 = 0,
40 consecutive PFD cycles of 10 ns or less must occur before
digital lock detect goes high. The recommended settings for
Bits[DB8:DB7] are listed in Table 7.
Table 7. Recommended LDF and LDP Bit Settings
Mode
Integer-N
Fractional-N, Low Noise Mode
Fractional-N, Low Spur Mode
Power-Down (PD)
The DB5 bit provides the programmable power-down mode.
Setting this bit to 1 performs a power-down. Setting this bit to 0
returns the synthesizer to normal operation. In software power-
down mode, the part retains all information in its registers. The
register contents are lost only if the supply voltages are removed.
When power-down is activated, the following events occur:
•
•
•
•
•
Charge Pump Three-State
Setting the DB4 bit to 1 puts the charge pump into three-state
mode. This bit should be set to 0 for normal operation.
Counter Reset
The DB3 bit is the reset bit for the R counter and the N counter
of the ADF4150HV. When this bit is set to 1, the RF synthesizer
N counter and R counter are held in reset. For normal opera-
tion, this bit should be set to 0.
Synthesizer counters are forced to their load state
conditions.
Charge pump is forced into three-state mode.
Digital lock detect circuitry is reset.
RF
Input registers remain active and capable of loading
and latching data.
OUT
buffers are disabled.
DB8 (LDF)
1
0
0
DB7 (LDP)
1
1
0