MK20DN512ZVMB10 FREESCALE [Freescale Semiconductor, Inc], MK20DN512ZVMB10 Datasheet - Page 28

• Manufacturer Part Number: MK20DN512ZVMB10
• Description: K20 Sub-Family Data Sheet
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Peripheral operating requirements and behaviors
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation
4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
6. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
7. Excludes any oscillator currents that are also consuming power while PLL is in operation.
8. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of
9. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
6.3.2 Oscillator electrical specifications
This section provides the electrical characteristics of the module.
6.3.2.1 Oscillator DC electrical specifications
28
Symbol
Symbol
I
J
t
DDOSC
pll_lock
mode).
(Δf
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
each PCB and results will vary.
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes
it is already running.
D
acc_pll
D
V
lock
DD
unl
dco_t
) over voltage and temperature should be considered.
PLL accumulated jitter over 1µs (RMS)
Lock entry frequency tolerance
Lock exit frequency tolerance
Lock detector detection time
Supply voltage
Supply current — low-power mode (HGO=0)
Description
Description
• f
• f
• 32 kHz
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz
vco
vco
= 48 MHz
= 100 MHz
Table 16. Oscillator DC electrical specifications
K20 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
Table 15. MCG specifications (continued)
Table continues on the next page...
± 1.49
± 4.47
1.71
Min.
Min.
—
—
—
—
—
—
—
—
—
1350
Typ.
Typ.
600
500
200
300
950
1.2
1.5
—
—
—
—
150 × 10
+ 1075(1/
± 2.98
± 5.97
f
Max.
pll_ref
Max.
3.6
—
—
—
—
—
—
—
—
Freescale Semiconductor, Inc.
)
-6
Unit
Unit
mA
mA
μA
μA
μA
nA
ps
ps
%
%
V
s
Notes
Notes
8
9
1