CY7C66113C-XC CYPRESS [Cypress Semiconductor], CY7C66113C-XC Datasheet - Page 25

• Manufacturer Part Number: CY7C66113C-XC
• Description: Full-Speed USB (12 Mbps) Peripheral Controller with Integrated Hub
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-08024 Rev. *B
Port 1 Interrupt Enable
Port 2 Interrupt Enable
Port 3 Interrupt Enable
10.0
The CY7C66113CC features a programmable sink current 8 bit port which is also known as DAC port. Each of these port I/O pins
have a programmable current sink. Writing a ‘1’ to a DAC I/O pin disables the output current sink (I
pin HIGH through an integrated 14-k
resistor is disabled. This causes the I
DAC port pin.
The amount of sink current for the DAC I/O pin is programmable over 16 values based on the contents of the DAC Isink Register
(Figure 10-3) for that output pin. DAC[1:0] are high current outputs that are programmable from 3.2 mA to 16 mA (typical).
DAC[7:2] are low current outputs, programmable from 0.2 mA to 1.0 mA (typical).
When the suspend bit in Processor Status and Control Register (Figure 15-1) is set, the Isink DAC block of the DAC circuitry is
disabled. Special care should be taken when the CY7C66113C device is placed in the suspend. The DAC Port Data
Register(Figure 10-2) should normally be loaded with all ‘1’s (Figure 15-1) before setting the suspend bit. If any of the DAC bits
Bit #
Bit Name
Read/Write
Reset
Bit #
Bit Name
Read/Write
Reset
Bit #
Bit Name
Read/Write
Reset
DAC Port
7
P1.7 Intr
Enable
W
0
7
P2.7 Intr
Enable
W
0
7
Reserved
W
0
Internal
Data Bus
6
P3.6 Intr Enable
CY7C66113C
only
W
0
Interrupt
Enable
Interrupt
Polarity
6
P1.6 Intr
Enable
W
0
6
P2.6 Intr
Enable
W
0
Internal
Buffer
sink
DAC Read
DAC Write
resistor. When a ‘0’ is written to a DAC I/O pin, the I
Data
Out
Latch
DAC to sink current to drive the output LOW. Figure 10-1 shows a block diagram of the
Figure 10-1. Block Diagram of a DAC Pin
5
P3.5 Intr Enable
CY7C66113C
only
W
0
5
P1.5 Intr
Enable
W
0
5
P2.5 Intr
Enable
W
0
Figure 9-10. Port 3 Interrupt Enable
Figure 9-8. Port 1 Interrupt Enable
Figure 9-9. Port 2 Interrupt Enable
Suspend
(Bit 3 of Register 0xFF)
Isink
Register
4
P1.4 Intr
Enable
W
0
4
P2.4 Intr
Enable
W
0
4
P3.4 Intr
Enable
W
0
4 bits
Isink
DAC
to Interrupt
Controller
3
P1.3 Intr
Enable
W
0
3
P2.3 Intr
Enable
W
0
3
P3.3 Intr
Enable
W
0
V
CC
Q1
14 k
2
P1.2 Intr
Enable
W
0
2
P2.2 Intr
Enable
W
0
2
P3.2 Intr
Enable
W
0
sink
DAC is enabled and the pull-up
I/O Pin
DAC
sink
1
P1.1 Intr
Enable
W
0
1
P2.1 Intr
Enable
W
0
1
P3.1 Intr
Enable
W
0
DAC) and drives the I/O
CY7C66013C
CY7C66113C
Page 25 of 61
ADDRESS 0x05
0
P1.0 Intr
Enable
W
0
ADDRESS 0x06
0
P2.0 Intr
Enable
W
0
ADDRESS 0x07
0
P3.0 Intr
Enable
W
0
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