CY7C66113C-XC CYPRESS [Cypress Semiconductor], CY7C66113C-XC Datasheet - Page 30

• Manufacturer Part Number: CY7C66113C-XC
• Description: Full-Speed USB (12 Mbps) Peripheral Controller with Integrated Hub
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-08024 Rev. *B
Bit 1: Receive Stop
Bit 0: I
14.0
The CY7C66x13C processor provides a hardware assisted parallel interface for bus widths of 8, 16, or 24 bits, to accommodate
data transfer with an external microcontroller or similar device. Control bits for selecting the byte width are in the HAPI/I
Configuration Register (Figure 12-1), bits 1 and 0.
Signals are provided on Port 2 to control the HAPI interface. Table 14-1 describes these signals and the HAPI control bits in the
HAPI/I
overridden. The Port 2 output pins are in CMOS output mode and Port 2 input pins are in input mode (open drain mode with Q3
OFF in Figure 9-1).
Table 14-1. Port 2 Pin and HAPI Configuration Bit Definitions
HAPI Read by External Device from CY7C66x13C:
In this case (see Figure 25-3), firmware writes data to the GPIO ports. If 16-bit or 24-bit transfers are being made, Port 0 should
be written last, since writes to Port 0 asserts the Data Ready bit and the DReadyPin to signal the external device that data is
available.
The external device then drives the OE and CS pins active (LOW), which causes the HAPI data to be output on the port pins.
When OE is returned HIGH (inactive), the HAPI/GPIO interrupt is generated. At that point, firmware can reload the HAPI latches
for the next output, again writing Port 0 last.
The Data Ready bit reads the opposite state from the external DReadyPin on pin P2[3]. If the DRDY Polarity bit is 0, DReadyPin
is active HIGH, and the Data Ready bit is active LOW.
HAPI Write by External Device to CY7C66x13C:
In this case (see Figure 25-4), the external device drives the STB and CS pins active (LOW) when it drives new data onto the
port pins. When this happens, the internal latches become full, which causes the Latch Empty bit to be deasserted. When STB
is returned HIGH (inactive), the HAPI/GPIO interrupt is generated. Firmware then reads the parallel ports to empty the HAPI
latches. If 16-bit or 24-bit transfers are being made, Port 0 should be read last because reads from Port 0 assert the Latch Empty
bit and the LatEmptyPin to signal the external device for more data.
The Latch Empty bit reads the opposite state from the external LatEmptyPin on pin P2[2]. If the LEMPTY Polarity bit is 0,
LatEmptyPin is active HIGH, and the Latch Empty bit is active LOW.
Pin
P2[2]
P2[3]
P2[4]
P2[5]
P2[6]
Bit
2
3
4
5
This bit is set when the slave is in receive mode and detects a stop bit on the bus. The Receive Stop bit is not set if the
firmware terminates the I
e.g. in receive mode if firmware sets the Continue bit and clears the ACK bit.
Set this bit to override GPIO definition with I
these pins are free to function as GPIOs. In I
of the GPIO configuration setting.
2
2
C Configuration Register. Enabling HAPI causes the GPIO setting in the GPIO Configuration Register (Figure 9-6) to be
C Enable
Hardware Assisted Parallel Interface (HAPI)
Name
LatEmptyPin
DReadyPin
STB
OE
CS
Name
Data Ready
Latch Empty
DRDY Polarity
LEMPTY Polarity
2
C transaction by not acknowledging the previous byte transmitted on the I
Direction
In
In
R/W
R
R
Out
Out
In
R/W
R/W
Description (Port 2 Pin)
Ready for more input data from external interface.
Output data ready for external interface.
Strobe signal for latching incoming data.
Output Enable, causes chip to output data.
Chip Select (Gates STB and OE).
Description (HAPI/I
Asserted after firmware writes data to Port 0, until OE driven LOW.
Asserted after firmware reads data from Port 0, until STB driven LOW.
Determines polarity of Data Ready bit and DReadyPin:
If 0, Data Ready is active LOW, DReadyPin is active HIGH.
If 1, Data Ready is active HIGH, DReadyPin is active LOW.
Determines polarity of Latch Empty bit and LatEmptyPin:
If 0, Latch Empty is active LOW, LatEmptyPin is active HIGH.
If 1, Latch Empty is active HIGH, LatEmptyPin is active LOW.
2
C-compatible function on the two I
2
C-compatible mode, the two pins operate in open drain mode, independent
2
C Configuration Register)
2
C-compatible pins. When this bit is cleared,
CY7C66013C
CY7C66113C
2
C-compatible bus,
Page 30 of 61
2
C
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