CY7C68000 CYPRESS [Cypress Semiconductor], CY7C68000 Datasheet - Page 6

• Manufacturer Part Number: CY7C68000
• Description: TX2 USB 2.0 UTMI Transceiver
• Manufacturer: CYPRESS [Cypress Semiconductor]

Table 5-1. Pin Descriptions (continued)
Document #: 38-08016 Rev. *E
SSOP QFN
25
22
21
28
29
30
5
8
7
18
15
14
54
21
22
23
56
1
LineState0
OpMode1
OpMode0
TXValid
TXReady
RXValid
RXActive
RXError
ValidH
Name
Output
Output
Output
Output
Output
Type
Input
Input
Input
I/O
[1]
Default
PRELIMINARY
Line State. These signals reflect the current state of the single-ended
receivers. They are combinatorial until a “usable” CLK is available then they
are synchronized to CLK. They directly reflect the current state of the
DPLUS (LineState0) and DMINUS (LineState1).
D- D+ Description
00–0: SE0
01–1: ‘J’ State
10–2: ‘K’ State
11–3: SE1.
Operational Mode. These signals select among various operational
modes:
10 Description
00–0: Normal Operation
01–1: Non-driving
10–2: Disable Bit Stuffing and NRZI encoding
11–3: Reserved.
Operational Mode. These signals select among various operational
modes:
10 Description
00–0: Normal Operation
01–1: Non-driving
10–2: Disable Bit Stuffing and NRZI encoding
11–3: Reserved.
Transmit Valid. Indicates that the data bus is valid. The assertion of Trans-
mit Valid initiates SYNC on the USB. The negation of Transmit Valid initiates
EOP on the USB. The start of SYNC must be initiated on the USB no less
than one or no more that two CLKs after the assertion of TXValid.
In HS (XcvrSelect = 0) mode, the SYNC pattern must be asserted on the
USB between 8- and 16-bit times after the assertion of TXValid is detected
by the Transmit State Machine.
In FS (Xcvr = 1), the SYNC pattern must be asserted on the USB no less
than one or more than two CLKs after the assertion of TXValid is detected
by the Transmit State Machine.
Transmit Data Ready. If TXValid is asserted, the SIE must always have
data available for clocking in to the TX Holding Register on the rising edge
of CLK. If TXValid is TRUE and TXReady is asserted at the rising edge of
CLK, the CY7C68000 will load the data on the data bus into the TX Holding
Register on the next rising edge of CLK. At that time, the SIE should immedi-
ately present the data for the next transfer on the data bus
Receive Data Valid. Indicates that the DataOut bus has valid data. The
Receive Data Holding Register is full and ready to be unloaded. The SIE is
expected to latch the DataOut bus on the clock edge.
Receive Active. Indicates that the receive state machine has detected
SYNC and is active.
RXActive is negated after a bit stuff error or an EOP is detected.
Receive Error.
0 Indicates no error.
1 Indicates that a receive error has been detected.
ValidH. This signal indicates that the high-order eight bits of a 16-bit data
word presented on the Data bus are valid. When DataBus16_8 = 1 and
TXValid = 0, ValidH is an output, indicating that the high-order receive data
byte on the Data bus is valid. When DataBus16_8 = 1 and TXValid = 1,
ValidH is an input and indicates that the high-order transmit data byte,
presented on the Data bus by the transceiver, is valid. When DataBus16_8
= 0, ValidH is undefined. The status of the receive low-order data byte is
determined by RXValid and are present on D0–D7.
Description
CY7C68000
.
Page 6 of 14