AD2S82 AD [Analog Devices], AD2S82 Datasheet - Page 14

• Manufacturer Part Number: AD2S82
• Description: Variable Resolution, Monolithic Resolver-to-Digital Converters
• Manufacturer: AD [Analog Devices]

AD2S81A/AD2S82A
For example, for a phase shift of 20 degrees, a shaft rotation of
22 rps and a reference frequency of 5 kHz, the converter will
exhibit an additional error of:
This effect can be eliminated by putting a phase shift in the
reference to the converter equivalent to the phase shift in the
resolver (see Connecting the Resolver section).
Note: Capacitive and inductive crosstalk in the signal and reference
leads and wiring can cause similar problems.
VELOCITY ERRORS
The signal at the INTEGRATOR O/P pin relative to the ANA-
LOG GND pin is an analog voltage proportional to the rate of
change of the input angle. This signal can be used to stabilize
servo loops or in the place of a velocity transducer. Although the
conversion loop of the AD2S81A/AD2S82A includes a digital
section, there is an additional analog feedback loop around the
velocity signal. This ensures against flicker in the digital posi-
tional output in both dynamic and static states.
A better quality velocity signal will be achieved if the following
points are considered:
1. Protection.
2. Reversion error*
3. Ripple and Noise.
*
Reversion error, or side-to-side nonlinearity, is a result of differences in the up and
down rates of the VCO.
The velocity signal should be buffered before use.
The reversion error can be nulled by varying one supply rail
relative to the other.
Noise on the input signals to the converter is the major cause of
noise on the velocity signal. This can be reduced to a minimum
if the following precautions are taken:
The resolver is connected to the converter using separate
twisted pair cable for the sine, cosine and reference signals.
Care is taken to reduce the external noise wherever possible.
An HF filter is fitted before the Phase-Sensitive Demodulator
(as described in the section HF FILTER).
A resolver is chosen that has low residual voltage, i.e., a small
signal in quadrature with the reference.
Components are selected to operate the AD2S81A/AD2S82A
with the lowest acceptable bandwidth.
Feedthrough of the reference frequency should be removed
by a filter on the velocity signal.
Maintenance of the input signal voltages at 2 V rms will
prevent LSB flicker at the positional output. The analog
feedback or hysteresis employed around the VCO and the
integrator is a function of the input signal levels (see Integra-
tor section).
22 20
5000
0.088 degrees
–14–
Following the preceding precautions will allow the user to use
the velocity signal in very noisy environments for example PWM
motor drive applications. Resolver/converter error curves may
exhibit apparent acceleration/deceleration at a constant velocity.
This results in ripple on the velocity signal of frequency twice
the input rotation.
CONNECTING THE RESOLVER
The recommended connection circuit is shown in Figure 9.
In cases where the reference phase relative to the input signals
from the resolver requires adjustment, this can be easily
achieved by varying the value of the resistor R2 of the HF filter
(see Figures 1a and 1b).
Assuming that R1 = R2 = R and C1 = C2 = C
and Reference Frequency =
by altering the value of R2, the phase of the reference relative to
the input signals will change in an approximately linear manner
for phase shifts of up to 10 degrees.
Increasing R2 by 10% introduces a phase lag of 2 degrees. De-
creasing R2 by 10% introduces a phase lead of 2 degrees.
R1
R2
S2
RESOLVER
PHASE LEAD = ARC TAN
Figure 9. Connecting the AD2S82A to a Resolver
TWISTED PAIR
SCREENED
CABLE
S4
S3
S1
Figure 10. Phase Shift Circuits
C
R
2
1
fRC
2
1
RC
PHASE LAG = ARC TAN 2
POWER RETURN
C3
R3
R
1
2
3
4
5
6
7
C
COS I/P
ANALOG
GND
SIN I/P
(e. g. OSC1758)
REF I/P
SIGNAL
GND
OSCILLATOR
AD2S82A
DIGITAL
fRC
GND
REV. B
31