HSP48908/883 INTERSIL [Intersil Corporation], HSP48908/883 Datasheet - Page 4

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HSP48908/883

Manufacturer Part Number
HSP48908/883
Description
Two Dimensional Convolver
Manufacturer
INTERSIL [Intersil Corporation]
Datasheet
Device Tested at: V
NOTES:
Clock Period
Clock Pulse Width
High
Clock Pulse Width Low
Data Input Setup Time
Data Input Hold Time
Clock to Data Out
Address Setup Time
Address Hold Time
Configuration Data
Setup Time
Configuration Data
Hold Time
LD Pulse Width
LD Setup Time
CIN7-0 Setup to CLK
CIN7-0 Hold to CLK
CS Setup to LD
CS Setup to LD
RESET Pulse Width
FRAME Setup to Clock
FRAME Pulse Width
EALU Setup Time
EALU Hold Time
HOLD Setup Time
HOLD Hold Time
Output Enable Time
6. This specification applies only to the case where the HSP48908/883 is being written to during an active convolution cycle. It must be met in order
7. While FRAME is an asynchronous signal, it must be deasserted a minimum of t
8. Transition is measured at 200mV from steady state voltage with loading as specified in test load circuit with C
9. AC Testing is performed as follows: Input levels (CLK input) 4.0V and 0V, input levels (all other inputs) 0V and 3.0V, timing reference levels
to achieve predictable results at the next rising clock edge. In most applications, the configuration data and coefficients are loaded
asynchronously and the t
data for a new frame.
(CLK) = 2.0V, (others) = 1.5V. Output load per test load circuit with C
PARAMETER
CC
= 5.0V 10%, T
SYMBOL
t
CYCLE
t
t
t
t
t
t
t
t
t
t
t
PWH
RPW
FPW
PWL
t
OUT
CDS
CDH
LPW
t
CSS
CSH
t
t
t
t
LCS
t
t
t
t
t
t
LCS
DS
DH
AH
CS
CH
EH
HS
HH
EN
AS
FS
ES
4
Specification may be disregarded.
A
TABLE 2. AC ELECTRICAL PERFORMANCE SPECIFICATIONS
= -55
NOTES
Note 6
Note 7
Note 8
o
C to 125
o
C (Note 9)
SUBGROUP
GROUP A
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
HSP48908/883
L
-55
-55
-55
-55
-55
-55
-55
-55
-55
-55
-55
-55
-55
-55
-55
-55
-55
-55
-55
-55
-55
-55
-55
-55
= 40pF. Output transition is measured at V
TEMP (
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
FS
o
ns prior to the rising clock edge which is to begin loading pixel
C)
125
125
125
125
125
125
125
125
125
125
125
125
125
125
125
125
125
125
125
125
125
125
125
125
MIN
37
15
15
16
15
17
15
30
17
37
25
37
15
13
-27 (27MHz)
0
0
0
0
0
0
0
2
-
-
MAX
19
19
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
L
MIN
50
20
20
17
15
20
20
37
20
50
30
50
17
14
= 40pF.
-20 (20MHz)
0
0
0
0
0
0
0
2
-
-
OH
1.5V and V
MAX
28
28
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
OL
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.5V.

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