hsp48908 Intersil Corporation, hsp48908 Datasheet
hsp48908
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hsp48908 Summary of contents
Page 1
... The pixel data path also includes an on-chip ALU for performing real-time arithmetic and logical pixel point operations. Data is provided to the HSP48908 in a raster scan noninterlaced fashion, and is internally buffered on images up to 1024 pixels wide for the convolution operation. ...
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... CAS04 CAS06 9 CAS03 8 CAS01 CAS02 DIN1 CASO0 5 DIN2 4 DIN5 3 DIN7 2 CIN0 1 CIN2 A 2 HSP48908 84 PIN PGA TOP VIEW DOUT1 GND DOUT5 DOUT6 DOUT8 CAS07 DOUT2 DOUT4 DOUT9 GND GND DOUT3 DOUT7 V CC GND V CC DIN0 DIN3 DIN4 DIN6 CIN1 CIN9 ...
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... EALU 28 CASI15 29 CASI14 30 CASI13 31 CASI12 32 3 HSP48908 84 LEAD PLCC TOP VIEW CASO6 73 CASO7 DOUT0 72 DOUT1 71 70 DOUT2 GND ...
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... CIN5 CIN6 CIN7 CIN8 CIN9 GND GND CLK HOLD EALU CASI15 CASI14 CASI13 CASI12 NC NC CASI11 4 HSP48908 100 LEAD MQFP TOP VIEW 100 ...
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... Block Diagram DATA DELAY - DIN0 - CIN0 - 9 REGISTER CONTROL FRAME RESET CASIO - ADDRESS DECODER LD CS CLK HOLD 5 HSP48908 ALU CASIO - ROW BUFFER -1 Z CASCADE MODE ALU - LOGIC - ...
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... Input and System Clock. Operations are synchronous with the rising edge of this clock signal. Pixel Data Input Bus. This bus is used to provide the 8-bit pixel input data to the HSP48908. The data must be provided in a synchronous fashion, and is latched on the rising edge of the CLK signal. ...
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... The HSP48908 has internal storage for two filter kernels and is capable of buffering two 1024 x 8-bit rows for true single chip operation at video frame rates. An 8-bit ALU ...
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... Initialization Register. This mode allows the use of external row buffers for convolving with row lengths longer than 1024 pixels. 8 HSP48908 8-BIt Multiplier Array The multiplier array consists of nine multipliers. Each multiplier forms the product of a filter coefficient with a OPERATION corresponding pixel in the input image. Input and coeffi ...
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... HSP48908 ADDRESS DECODE LD CS CIN0 - 9 ALU MICROCODE REGISTER LMC INITIALIZATION REGISTER CAS ROW LENGTH REGISTER EOR CRO CR1 S Q ENCR1 ENCRO R Q FIGURE 1. CONTROL LOGIC BLOCK DIAGRAM 9 ENCR1 ENCR0 CAS CR1 CR0 ...
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... CS and LD inputs. Address Decoder The address decoder (see Figure 1) is used for writing to the control logic of the HSP48908. Loading an Internal Register is done by selecting the Destination Register with the A0-2 address lines, placing the data on CIN0-9, asserting the CS and LD control lines. When either goes high, the data on the CIN0-9 lines is latched into the Addressed Register ...
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... FIGURE 2. HOLD OPERATION RESET The RESET signal initializes all internal flip flops and registers in the HSP48908 asynchronous signal, and the convolver will remain in the reset state as long as RESET is asserted. On reset, all internal registers are set to zero or their default values, and all outputs are forced low. ...
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... Single Chip Mode A single HSP48908 can be used to perform convolution on 8-bit image data with row lengths up to 1024. A block diagram of this configuration is shown in Figure 3. In this mode of operation, the image data is input into the DlN0-7 bus in a raster scan order starting with the upper left pixel ...
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... Figure 5 illustrates the use of two HSP48908s to perform ker- nel convolution frame. In this case, the cascade mode control bit (Bit 0) of both Initialization Registers are set to a ‘ ...
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... N image. CASO0 - 7 The coefficient mask is again distributed among the four HSP48908’s. The width of the DOUT path to be used in this case is dependent on the amount of resolution required and the amount of growth expected at the output. ...
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... Input Capacitance Output Capacitance NOTES: 2. Power supply current is proportional to operating frequency. Typical rating for I 3. Not tested, but characterized at initial design and at major process/design changes. 15 HSP48908 Thermal Information Thermal Resistance (Typical, Note 1) +0.5V MQFP Package . . . . . . . . . . . . . . . . . . CC PLCC Package . . . . . . . . . . . . . . . . . . ...
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... Output Fall Time NOTES: 4. This specification applies only to the case where the HSP48908 is being written to during an active convolution cycle. It must be met in order to achieve predictable results at the next rising clock edge. In most applications, the configuration data and coefficients are loaded asynchronously and the T Specification may be disregarded ...
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... Includes stray and jig capacitance. 10. Switch S Open for I and I 1 CCSB CCOP Timing Waveforms CLK DIN0 - 7, CASI0 - 15 DOUT0 - 19, CASO0 - 7 CIN0 - 7 (TO ALU REGISTER) CLK EALU FIGURE 9. EALU TIMING 17 HSP48908 S 1 DUT EQUIVALENT CIRCUIT Tests. t CYCLE t PWL FIGURE 8. FUNCTIONAL TIMING DOUT0 - 19 1.5V ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 18 HSP48908 t CSS t ...