PCF8562TT-2 NXP [NXP Semiconductors], PCF8562TT-2 Datasheet - Page 20

• Manufacturer Part Number: PCF8562TT-2
• Description: Universal LCD driver for low multiplex rates
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
PCF8562
Product data sheet
7.10.3 RAM writing in 1:3 multiplex drive mode
7.10.4 Output bank selector
In 1:3 multiplex drive mode, the RAM is written as shown in
well).
Table 6.
Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are not connected to any elements on the display.
If the bit at position BP2/S2 would be written by a second byte transmitted, then the
mapping of the segment bits would change as illustrated in
Table 7.
Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are connected to elements on the display.
In the case described in
BP2/S8 etc. have to be connected to elements on the display. This can be achieved by a
combination of writing and rewriting the RAM like follows:
Depending on the method of writing to the RAM (standard or entire filling by rewriting),
some elements remain unused or can be used, but it has to be considered in the module
layout process as well as in the driver software design.
The output bank selector (see
address for transfer to the display register. The actual row selected depends on the
particular LCD drive mode in operation and on the instant in the multiplex sequence.
Display RAM
bits (rows)/
backplane
outputs (BPn)
0
1
2
3
Display RAM
bits (rows)/
backplane
outputs (BPn)
0
1
2
3
•
•
•
•
•
In the first write to the RAM, bits a7 to a0 are written.
In the second write, bits b7 to b0 are written, overwriting bits a1 and a0 with bits b7
and b6.
In the third write, bits c7 to c0 are written, overwriting bits b1 and b0 with bits c7 and
c6.
In 1:4 multiplex mode, all RAM addresses of row 0 are selected, these are followed by
the content of row 1, 2, and then 3
In 1:3 multiplex mode, rows 0, 1, and 2 are selected sequentially
Standard RAM filling in 1:3 multiplex drive mode
Entire RAM filling by rewriting in 1:3 multiplex drive mode
All information provided in this document is subject to legal disclaimers.
Display RAM addresses (columns)/segment outputs (Sn)
0
a7
a6
a5
-
Display RAM addresses (columns)/segment outputs (Sn)
0
a7
a6
a5
-
Rev. 6 — 16 June 2011
1
a4
a3
a2
-
1
a4
a3
a2
-
Table 7
Table
2
a1
a0
-
-
2
a1/b7 b4
a0/b6 b3
b5
-
the RAM has to be written entirely and BP2/S2, BP2/S5,
14) selects one of the four rows per display RAM
3
b7
b6
b5
-
3
b2
-
Universal LCD driver for low multiplex rates
4
b4
b3
b2
-
4
b1/c7 c4
b0/c6 c3
c5
-
5
b1
b0
-
-
5
c2
-
d5
6
c7
c6
c5
-
6
c1/d7 d4
c0/d6 d3
-
Table
Table 6
7
c4
c3
c2
-
7
d2
-
7.
(see
8
c1
c0
-
-
8
d1/e7 e4
d0/e6 e3
e5
-
PCF8562
© NXP B.V. 2011. All rights reserved.
Figure 12
9
d7
d6
d5
-
9
e2
-
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