PCF8562TT-2 NXP [NXP Semiconductors], PCF8562TT-2 Datasheet - Page 25

• Manufacturer Part Number: PCF8562TT-2
• Description: Universal LCD driver for low multiplex rates
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
8. Characteristics of the I
PCF8562
Product data sheet
8.1 Bit transfer
8.2 START and STOP conditions
8.3 System configuration
The I
The two lines are a Serial DAta Line (SDA) and a Serial CLock line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor when connected to the output
stages of a device. Data transfer may be initiated only when the bus is not busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as a control signal (see
Both data and clock lines remain HIGH when the bus is not busy.
A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START
condition - S.
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition - P (see
A device generating a message is a transmitter, a device receiving a message is the
receiver. The device that controls the message is the master and the devices which are
controlled by the master are the slaves (see
Fig 13. Bit transfer
Fig 14. Definition of START and STOP conditions
2
C-bus is for bidirectional, two-line communication between different ICs or modules.
SDA
SCL
START condition
All information provided in this document is subject to legal disclaimers.
2
SDA
SCL
Figure
C-bus
S
Rev. 6 — 16 June 2011
14).
data valid
data line
stable;
Figure
Universal LCD driver for low multiplex rates
Figure
allowed
change
of data
13).
15).
STOP condition
mba607
P
PCF8562
© NXP B.V. 2011. All rights reserved.
mbc622
SDA
SCL
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