PCF8563BS NXP [NXP Semiconductors], PCF8563BS Datasheet - Page 12

• Manufacturer Part Number: PCF8563BS
• Description: Real-time clock/calendar
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
PCF8563_6
Product data sheet
Fig 8.
POR override sequence
SDA
SCL
power up
7.8 Power-On Reset (POR) override
8 ms
Operation example:
Repeat steps 7 and 8 for additional increments.
The POR duration is directly related to the crystal oscillator start-up time. Due to the long
start-up times experienced by these types of circuits, a mechanism has been built in to
disable the POR and hence speed up on-board test of the device. The setting of this mode
requires that the I
Figure
Once the Override mode has been entered, the device immediately stops being reset and
normal operation may commence i.e. entry into the EXT_CLK test mode via I
access. The Override mode may be cleared by writing a logic 0 to TESTC. TESTC must
be set to logic 1 before re-entry into the Override mode is possible. Setting TESTC to
logic 0 during normal operation has no effect except to prevent entry into the POR
override mode.
Table 25
Table 25.
Address Register name
00h
01h
02h
03h
04h
1. Set EXT_CLK test mode (control_status_1, bit TEST1 = 1)
2. Set STOP (control_status_1, bit STOP = 1)
3. Clear STOP (control_status_1, bit STOP = 0)
4. Set time registers to desired value
5. Apply 32 clock pulses to CLKOUT
6. Read time registers to see the first change
7. Apply 64 clock pulses to CLKOUT
8. Read time registers to see the second change
8. All timings are required minimums.
shows the register reset values.
control_status_1
control_status_2
VL_seconds
minutes
hours
500 ns
Register reset value
2
C-bus pins, SDA and SCL, be toggled in a specific order as shown in
Rev. 06 — 21 February 2008
2000 ns
Bit 7
0
x
1
1
x
[1]
Bit 6
0
x
x
x
x
Bit 5
0
0
x
x
x
Bit 4
0
0
x
x
x
override active
Bit 3
1
0
x
x
x
Real-time clock/calendar
Bit 2
0
0
x
x
x
PCF8563
© NXP B.V. 2008. All rights reserved.
mgm664
Bit 1
0
0
x
x
x
2
C-bus
Bit 0
0
0
x
x
x
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