PCA85133 NXP [NXP Semiconductors], PCA85133 Datasheet
PCA85133
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PCA85133 Summary of contents
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... Universal LCD driver for low multiplex rates Rev. 1 — 23 October 2009 1. General description The PCA85133 is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD) multiplexed LCD containing up to four backplanes and segments and can easily be cascaded for larger LCD applications. The PCA85133 is compatible with most ...
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... Description 1.07 1.07 Marking codes Rev. 1 — 23 October 2009 PCA85133 Universal LCD driver for low multiplex rates [1] Delivery form 0.40 mm chip with hard bumps in tray PCA85133 0.40 mm chip with soft bumps in tray Marking code PC85133-1 PC85133-1 © NXP B.V. 2009. All rights reserved. Version PCA85133 ...
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... LCD BIAS GENERATOR V SS CLK CLOCK SELECT AND TIMING SYNC OSC OSCILLATOR FF SCL INPUT FILTERS SDA Fig 1. Block diagram of PCA85133 PCA85133_1 Product data sheet BP0 BP1 BP2 BP3 BACKPLANE OUTPUTS LCD VOLTAGE SELECTOR DISPLAY CONTROL PCA85133 BLINKER TIMEBASE COMMAND POWER-ON DECODE ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Viewed from active side. For mechanical details, see Fig 2. Pin configuration of PCA85133 6.2 Pin description Table 3. Symbol SDAACK SDA SCL CLK V DD SYNC OSC FF A0, A1 and A2 SA0 [ LCD BP2, BP0, BP3 and BP1 S0 to S79 ...
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... LCDs. It can directly drive any static or multiplexed LCD containing up to four backplanes and segments. The display configurations possible with the PCA85133 depend on the required number of active backplane outputs. A selection of display configurations is shown in All of the display configurations can be implemented in a typical system as shown in Figure 3 ...
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... NXP Semiconductors 7.1 Power-on reset At power-on the PCA85133 resets to the following starting conditions: • All backplane and segment outputs are set to V • The selected drive mode is 1:4 multiplex with • Blinking is switched off • Input and output bank selectors are reset • ...
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... Universal LCD driver for low multiplex rates to V and is determined from off(RMS 2.449V = off RMS off RMS 4 3 --------------------- - 2.309V = off RMS 3 1 when bias is used. 3 PCA85133 Equation 1 (1) Equation 2: (2) Equation 3: (3) LCD © NXP B.V. 2009. All rights reserved ...
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... V ( (t) V (t). state2 ( BP0 off(RMS) Static drive mode waveforms Rev. 1 — 23 October 2009 PCA85133 Universal LCD driver for low multiplex rates Figure T fr LCD segments state 1 state 2 (on) (off) 013aaa207 © NXP B.V. 2009. All rights reserved ...
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... NXP Semiconductors 7.4.2 1:2 Multiplex drive mode When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The PCA85133 allows the use of Figure 6. Fig 5. PCA85133_1 Product data sheet 1 1 bias LCD V /2 BP0 LCD LCD BP1 V /2 LCD LCD ...
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... V (t) V (t). state2 Sn BP1 V = 0.333V . off(RMS) LCD Waveforms for the 1:2 multiplex drive mode with Rev. 1 — 23 October 2009 PCA85133 Universal LCD driver for low multiplex rates T fr LCD segments state 1 state 2 (a) Waveforms at driver. (b) Resultant waveforms 013aaa209 at LCD segment. 1 bias 3 © NXP B.V. 2009. All rights reserved. ...
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... V (t). state2 Sn BP1 V = 0.333V . off(RMS) LCD Waveforms for the 1:3 multiplex drive mode with Rev. 1 — 23 October 2009 PCA85133 Universal LCD driver for low multiplex rates T fr LCD segments state 1 state 2 013aaa210 at LCD segment. 1 bias 3 © NXP B.V. 2009. All rights reserved ...
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... V (t). state2 Sn BP1 V = 0.333V . off(RMS) LCD Waveforms for the 1:4 multiplex drive mode with Rev. 1 — 23 October 2009 PCA85133 Universal LCD driver for low multiplex rates T fr state 1 state 2 013aaa211 at LCD segment. 1 bias 3 © NXP B.V. 2009. All rights reserved. LCD segments ...
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... NXP Semiconductors 7.5 Oscillator The internal logic and the LCD drive signals of the PCA85133 are timed by a frequency f which either is derived from the built-in oscillator frequency f clk f = clk or equals an external clock frequency clk 7.5.1 Internal clock The internal oscillator is enabled by connecting pin OSC to V from pin CLK provides the clock signal for any cascaded PCA85133 in the system ...
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... The display RAM bitmap shows the direct relationship between the display RAM addresses and the segment outputs and between the bits in a RAM word and the backplane outputs. Display RAM bitmap Rev. 1 — 23 October 2009 PCA85133 Universal LCD driver for low multiplex rates Figure 9 shows rows which ...
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LCD segments LCD backplanes S a n+2 BP0 n+3 n+1 static n+5 n n+6 BP0 1 ...
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... NXP Semiconductors When display data is transmitted to the PCA85133, the received display bytes are stored in the display RAM in accordance with the selected LCD drive mode. The data is stored as it arrives and does not wait for the acknowledge cycle as with the commands. Depending on the current multiplex drive mode, data is stored singularly, in pairs, triples or quadruples. To illustrate the fi ...
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... In static mode, row 0 is selected The PCA85133 includes a RAM bank switching feature in the static and 1:2 multiplex drive modes. In the static drive mode, the bank-select command may request the contents of row selected for display instead of the contents of row 0. In the 1:2 mode, the contents of rows 2 and 3 may be selected instead of rows 0 and 1 ...
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... The two lines are a Serial Data line (SDA) and a Serial Clock Line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. By connecting pin SDAACK to pin SDA on the PCA85133, the SDA line becomes fully 2 I C-bus compatible. In COG applications where the track resistance from the SDAACK pin to the system SDA line can be signifi ...
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... Product data sheet SDA SCL data line stable; data valid S START condition MASTER SLAVE TRANSMITTER/ TRANSMITTER/ RECEIVER RECEIVER Rev. 1 — 23 October 2009 PCA85133 Universal LCD driver for low multiplex rates Figure 11). change of data allowed mba607 Figure 12. P STOP condition SLAVE MASTER TRANSMITTER/ ...
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... C-bus 2 C-bus slave receiver. It does not initiate I 2 C-bus master receiver. The only data output from the PCA85133 are which defines the hardware subaddress 0. In multiple device SS Rev. 1 — 23 October 2009 PCA85133 Universal LCD driver for low multiplex rates Figure 14 ...
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... Two I C-bus slave addresses (0111 000 and 0111 001) are reserved for the PCA85133. The least significant bit of the slave address is bit R/W. The PCA85133 is a write-only device. It will not respond to a read access, so this bit should always be logic 0. The second bit of the slave address is defined by the level tied at input SA0. Two types of PCA85133 can be distinguished on the same I • ...
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... Both data pointer and subaddress counter are automatically updated. The acknowledgement after each byte is made only by the (A0, A1, and A2) addressed PCA85133. After the last display byte, the I Alternatively a START may be asserted to RESTART an I PCA85133_1 Product data sheet ...
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... NXP Semiconductors 7.17 Command decoder The command decoder identifies command bytes that arrive on the I commands available to the PCA85133 are defined in Table 9. Command Bit mode-set load-data-pointer device-select bank-select blink-select Table 10. Bit [1] The possibility to disable the display allows implementation of blinking under external control. ...
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... RAM banks BF[1:0] blink frequency selection 00 off Table 7. Rev. 1 — 23 October 2009 PCA85133 Universal LCD driver for low multiplex rates [1] Section 7.13 and Section 7.14. 1:2 multiplex RAM bits 0 and 1 RAM bits 2 and 3 RAM bits 0 and 1 RAM bits 2 and 3 [1] [2] © ...
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... Product data sheet V DD FF, A0, A1 LCD BP0, BP1, BP2, BP3 S79 V SS Rev. 1 — 23 October 2009 PCA85133 Universal LCD driver for low multiplex rates SCL, SDA, SDAACK LCD V SS © NXP B.V. 2009. All rights reserved. ...
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... Ref. 7 “JESD78” = +95 C). Rev. 1 — 23 October 2009 PCA85133 Universal LCD driver for low multiplex rates ) is off, or vice versa. This may cause unwanted DD and V must be applied or removed together. LCD DD ...
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... 0 pin BPx bpl on pin Sx sgm LCD on pin BPx on pin external clock with 50 % duty factor Rev. 1 — 23 October 2009 PCA85133 Universal LCD driver for low multiplex rates Min Typ 1.8 - 2.5 - 2.5 - 2.5 - 1.0 1 ...
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... PCA85133_1 Product data sheet = 2 8 +95 C; unless otherwise specified. LCD amb f clk f = --------- . Rev. 1 — 23 October 2009 PCA85133 Universal LCD driver for low multiplex rates Conditions Min Typ [1][2] pin 1440 1970 DD [1][2] pin 1920 2640 SS pin ...
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... CLK SYNC t PD(SYNC_N) t SYNC_NL t PD(drv BUF LOW t HD;STA C-bus timing waveforms Rev. 1 — 23 October 2009 PCA85133 Universal LCD driver for low multiplex rates t clk( HD;DAT t HIGH t SU;STA © NXP B.V. 2009. All rights reserved ...
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... NXP Semiconductors 12. Application information 12.1 Cascaded operation In large display configurations PCA85133 can be recognized on the same 2 I C-bus by using the 3-bit hardware subaddress (A0, A1, and A2) and the programmable 2 I C-bus slave address (SA0). Table 18. Cluster 1 2 When cascaded PCA85133 are synchronized, they can share the backplane signals from one of the devices in the cascade ...
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... A PCA85133 asserts the SYNC line at the onset of its last active backplane signal and monitors the SYNC line at all other times. If synchronization in the cascade is lost restored by the first PCA85133 to assert SYNC. The timing relationships between the backplane waveforms and the SYNC signal ...
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... NXP Semiconductors Fig 21. Synchronization of the cascade for the various PCA85133 drive modes The contact resistance between the SYNC pins of cascaded devices must be controlled. If the resistance is too high, then the device will not be able to synchronize properly. This is particularly applicable to COG applications. resistance. ...
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... Bare die description 13.1 General description Table 20. Type number PCA85133U/2DA/Q1 PCA85133U/2DB/Q1 [1] Pressure of diamond head 13.2 Alignment marks Fig 22. Alignment marks of PCA85133 Table 21. All x/y coordinates represent the position of the REF point (see (x the chip; see Symbol S1 C1 PCA85133_1 Product data sheet ...
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... Rev. 1 — 23 October 2009 PCA85133 Universal LCD driver for low multiplex rates Description [ C-bus acknowledge output [ C-bus serial data input 2 I C-bus serial clock input clock input/output supply voltage ...
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... Rev. 1 — 23 October 2009 PCA85133 Universal LCD driver for low multiplex rates Description LCD segment output © NXP B.V. 2009. All rights reserved ...
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... Rev. 1 — 23 October 2009 PCA85133 Universal LCD driver for low multiplex rates Description LCD segment output LCD backplane output [2] dummy pad © NXP B.V. 2009. All rights reserved ...
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... Product data sheet Bump locations …continued Figure 23. Bump 1846.35 436.5 - 1953 436.5 - 1930.05 436.5 but are not tested. SS Rev. 1 — 23 October 2009 PCA85133 Universal LCD driver for low multiplex rates Description dummy pad Section 7.16. © NXP B.V. 2009. All rights reserved ...
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... max 0.018 0.388 mm nom 0.40 0.015 0.385 0.0338 min 0.012 0.382 Note 1. Dimension not drawn to scale. Outline version IEC PCA85133 - - - Fig 23. Bare die outline of PCA85133 PCA85133_1 Product data sheet PC85133 detail scale (1) (1) (1) ( ...
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... All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that all normal precautions are taken as described in JESD625-A , IEC 61340-5 or equivalent standards. 16. Packing information 16.1 Tray information for PCA85133 y Fig 24. Tray details for PCA85133 PCA85133_1 Product data sheet 2.1 3.1 1.1 1.2 2 ...
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... The orientation of the pocket is indicated by the position of the IC type name on the die surface with respect to the chamfer on the upper left corner of the tray (see Refer to the bump location diagram (see type name on the die surface. Fig 25. Tray alignment for PCA85133 tray PCA85133_1 Product data sheet Tray dimensions of PCA85133 tray 24 ...
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... Integrated Circuit Indium Tin Oxide Liquid Crystal Display Machine Model Random Access Memory Resistance-Capacitance Root Mean Square 2 C-bus specification and user manual Rev. 1 — 23 October 2009 PCA85133 Universal LCD driver for low multiplex rates © NXP B.V. 2009. All rights reserved ...
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... Revision history Table 25. Revision history Document ID Release date PCA85133_1 20091023 PCA85133_1 Product data sheet Universal LCD driver for low multiplex rates Data sheet status Change notice Product data sheet - Rev. 1 — 23 October 2009 PCA85133 Supersedes - © NXP B.V. 2009. All rights reserved ...
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... Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com Rev. 1 — 23 October 2009 PCA85133 Universal LCD driver for low multiplex rates © NXP B.V. 2009. All rights reserved ...
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... PCA85133 Universal LCD driver for low multiplex rates Bare die description . . . . . . . . . . . . . . . . . . . . 33 General description . . . . . . . . . . . . . . . . . . . . 33 Alignment marks . . . . . . . . . . . . . . . . . . . . . . 33 Bump locations Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 38 Handling information . . . . . . . . . . . . . . . . . . . 39 Packing information . . . . . . . . . . . . . . . . . . . . 39 Tray information for PCA85133 . . . . . . . . . . . 39 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 41 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Revision history . . . . . . . . . . . . . . . . . . . . . . . 42 Legal information . . . . . . . . . . . . . . . . . . . . . . 43 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 43 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Disclaimers Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Contact information ...