PCA85133 NXP [NXP Semiconductors], PCA85133 Datasheet - Page 18

• Manufacturer Part Number: PCA85133
• Description: Universal LCD driver for low multiplex rates
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
2.
PCA85133_1
Product data sheet
For further information, please consider the NXP application note:
7.16 Characteristics of the I
Table 7.
An additional feature is for an arbitrary selection of LCD segments to blink. This applies to
the static and 1:2 multiplex drive modes and can be implemented without any
communication overheads. By means of the output bank selector, the displayed RAM
banks are exchanged with alternate RAM banks at the blink frequency. This mode can
also be specified by the blink-select command.
In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of
LCD segments can blink by selectively changing the display RAM data at fixed time
intervals.
If the entire display can blink at a frequency other then the typical blink frequency. This
can be effectively performed by resetting and setting the display enable bit E at the
required rate using the mode-set command (see
The I
The two lines are a Serial Data line (SDA) and a Serial Clock Line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor when connected to the output
stages of a device. Data transfer may be initiated only when the bus is not busy.
By connecting pin SDAACK to pin SDA on the PCA85133, the SDA line becomes fully
I
to the system SDA line can be significant, possibly a voltage divider is generated by the
bus pull-up resistor and the Indium Tin Oxide (ITO) track resistance. As a consequence it
may be possible that the acknowledge generated by the PCA85133 can’t be interpreted
as logic 0 by the master. In COG applications where the acknowledge cycle is required, it
is therefore necessary to minimize the track resistance from the SDAACK pin to the
system SDA line to guarantee a valid LOW level.
By separating the acknowledge output from the serial data line (having the SDAACK open
circuit) design efforts to generate a valid acknowledge level can be avoided. However, in
that case the I
acknowledge cycle.
The following definition assumes SDA and SDAACK are connected and refers to the pair
as SDA.
Blink mode
off
1
2
3
2
C-bus compatible. In COG applications where the track resistance from the SDAACK pin
2
C-bus is for bidirectional, two-line communication between different ICs or modules.
Blink frequencies
Operating mode ratio
-
---------
----------- -
1536
----------- -
3072
768
2
f
f
f
C-bus master has to be set up in such a way that it ignores the
clk
clk
clk
2
Rev. 1 — 23 October 2009
2
C-bus
Ref. 1
Blink frequency with respect to f
f
blinking off
2.5
1.3
0.6
clk
“AN10170”.
= 1.970 kHz
Universal LCD driver for low multiplex rates
Table
10).
f
blinking off
3.5
1.7
0.9
clk
= 2.640 kHz
PCA85133
clk
© NXP B.V. 2009. All rights reserved.
(typical)
18 of 44
Unit
Hz
Hz
Hz
Hz