CDP68HC68S1M INTERSIL [Intersil Corporation], CDP68HC68S1M Datasheet - Page 8

• Manufacturer Part Number: CDP68HC68S1M
• Description: Serial Multiplexed Bus Interface
• Manufacturer: INTERSIL [Intersil Corporation]

ther reaching the bus. This will happen, as stated in the “Pri-
oritization” section, when a micro with a higher priority
address/ID byte attempts “simultaneous” transmission (actu-
ally, i.e. within a time window of 1/4 bit time).That micro, with
a higher priority ID byte, is obviously sending a 0-bit and its
reflected byte matches the byte it is sending. Not detecting a
collision, it continues to transmit its message, while the lower
priority MCU is cut off from transmitting on the bus. The
lower priority micro will be inhibited from transmitting on the
bus until the message presently on the bus has ended
(EOM = “End of Message” condition).
End of Message Condition
After transmitting the last byte of a message, the transmitting
MCU must generate an End of Message (EOM) condition.
An EOM condition is defined as a 10-bit length idle condi-
tion, i.e., the bus must remain idle (logic1) for a period of 10-
bit times (1280 internal clock periods). This can be done by
merely creating a 10-bit delay in MCU software.
Start Bit Arbitration Detection
Arbitration, as discussed above, is only necessary when two
or more micros attempt to transmit within 1/4 bit time (32
internal clock periods) of each other. Otherwise, once a
micro begins a transmission on the differential data bus, all
DIFFERENTIAL
ALL CONTROL
ALL IDLE
USER #1
USER #3
USER#2
PINS
XMIT #1
XMIT #2
XMIT #3
REC #2
REC #3
REC#1
PINS
BUS
START
BIT
NOTES:
(6)
1. USER #1 is note transmitting + marking.
2. Point at which USER #2 loses bus arbitration.
3. Point at which USER #3 loses bus arbitration.
4. Point at which USER #3 loses bus arbitration.
5. This ‘1’ bit is not overridden by the ‘0’ bits from users 2 and 3 because both users 2 and 3 have previ-
6. The control pin on the transmitting node goes low earlier in both SPI modes (it is pulled low by micro).
7. The control pin remains low until the end of the last data bit of the 2 byte set when using the buffered
ously been blocked from bus access due to data collisions.
SPI mode, but goes high at the middle of the last data bit in other modes.
0
0
0
0
0
0
0
0
FIGURE 6. EXAMPLE OF THE SCI CHIP OPERATING DURING BUS ARBITRATION
(3)
1
0
0
0
0
1
0
0
ID BYTE FOR A MESSAGE
(2)
2
0
0
1
0
0
0
0
3
1
1
0
1
0
1
1
4
0
0
0
0
0
0
0
(5)
5
1
1
0
1
0
1
1
6
0
0
1
0
0
0
0
7
0
0
0
0
0
0
0
STOP
CDP68HC68S1
(7)
BIT
10 IDLE BITS
6-91
other SBl chips sense the start bit and inhibit their microcom-
puters from transmitting (again, after a 32 clock period arbi-
tration window delay). Once the arbitration detector circuit
has blocked an MCU’s transmission, access to the bus will
be blocked until an End of Message condition.
Start of Message Delay
In order to properly synchronize various MCU’s (which may
be using different modes of operation) for impartial arbitra-
tion, each node must delay 2-bit times (256 internal clock
periods) after detecting the IDLE signal drop low before
transmitting, i.e., before the start bit of the next message
reaches the bus. When using the SPI or Buffered SPl
modes, this delay is automatically designed into the SBl
chip. However, when using the SCl mode, the MCU must
support this required delay. Fortunately, 68HC05 microcom-
puters using the SCI port will inherently experience a delay
between the time that the SCl data register is loaded and the
time that the start bit actually appears on the SCl port trans-
mit pin (TxD). At a baud rate of 7812.5 bps this delay can be
as long as 256 SBl chip internal clock periods. If this is so,
then the user MCU does not have to worry about providing
this delay.
(1)
START
BIT
(6)
ID BYTE FOR A DIFFERENT MESSAGE
0
0
0
0
0
0
(4)
0
0
0
0
1
1
1
1
1
1
2
0
0
0
0
0
0
3
4
0
0
0
0
0
0
0
0
0
0
5
1
1
1
1
1
6
0
0
0
0
7
0
STOP
BIT
(7)
10 IDLE BITS