CDP68HC68S1M INTERSIL [Intersil Corporation], CDP68HC68S1M Datasheet - Page 9

• Manufacturer Part Number: CDP68HC68S1M
• Description: Serial Multiplexed Bus Interface
• Manufacturer: INTERSIL [Intersil Corporation]

Idle Detection
An idle detector circuit is used to detect when the differential bus
is in the idle condition, i.e., no user microcomputer has control of
the bus and the bus is sitting at a mark condition (a logic one).
The idle detector senses a received stop bit and delays for a
short idle period of 10-bit times, during which the bus must
remain idle. The idle output pin is then set to a logic zero (true). It
is later set to a logic one by receiving a start bit. During the 10-bit
time delay, if a non-idle condition such as noise is detected on the
bus, the delay period counter will be restarted.
Due to the 10-bit time idle delay period, once an MCU wins
bus arbitration, it should send the next data byte to be trans-
mitted within a period of 10-bit times (1280 internal clock
periods). Each subsequent data byte to be sent should also
not exceed the interbyte maximum of 10-bit times. If this
maximum is exceeded, all SBlC chips will have detected the
idle condition and now pull their idle lines low and reset their
bus arbitration and collision detection circuits, thereby allow-
ing other SBl chips with messages to send to arbitrate for the
bus. Figure 6 shows the detailed operation of the serial bus
interface chip during bus arbitration. This example shows the
arbitration of a single byte (e.g. the address/ID byte) from
three different user microcomputers. Two full arbitration
cycles are shown.
Break Generator
A request for arbitration can be generated by a node that
needs to interrupt transmission of a long data string. This
can be accomplished by forcing the SBlC’s IDLE pin to a
logic zero; this forces a data collision (by sending 0-bits)
after three data bytes have been transmitted, and the trans-
mitting MCU is required to detect this break condition and
stop transmitting. It is, however, allowed to re-arbitrate for the
bus and the interrupting mode may not generate a second
break condition if it loses arbitration.
Using the CDP68HC68S1
Following are some hardware and software recommenda-
tions for using CDP68HC68S1 Serial Bus Interface Chip.
Requirements may vary depending upon the user’s system
configuration.
Hardware (General)
The differential bus lines (BUS+ and BUS-) must be termi-
nated with external resistors as shown in Figure 4. This
applies, however, only to one node (an MCU/SBlC pair)
along the bus. Since all SBl chips are wired in parallel across
the network bus, there is no need for additional 13K bias
resistors at each node. The 120
should, however, be present at two nodes if the network
does indeed contain two or more nodes. The 120
provides the voltage drop across which the SBl chip senses
logic zero and logic 1-bits. If two nodes each utilize 120 ter-
mination resistors as shown in Figure 7A, the effective resis-
tance across the BUS+ and BUS- pins drop to 60 total (due
to the parallel wiring method). Any less resistance would not
provide an ample voltage drop for the receiver cell op amp to
sense. Following these guidelines, typical systems might
look like those shown in Figure 7.
termination resistors
CDP68HC68S1
resistor
6-92
Software (General)
Although each user’s protocol may vary, the following gen-
eral procedure should be followed when using the SBl chip
in any mode:
When a microcomputer is preparing to transmit a message it
should monitor the SBlC’s IDLE pin and wait for it to go low
(logic zero) indicating the bus is idle. Then the MCU
attempts to transmit the first byte (preferably an Address/ID
byte). If no other MCUs are transmitting at this time, or if this
MCU has the highest priority ID byte, the SBI chip’s collision
detector circuit will permit transmission.
The microcomputer must then confirm transmission by read-
ing the byte reflected back from the bus. If this byte matches
the byte transmitted then the MCU has gained control of the
bus and may continue to transmit the remainder of the mes-
sage (if any).
If the reflected byte does not match the ID byte sent then the
MCU has not gained control of the bus and may not pres-
ently transmit. It should, however, check the reflected ID
byte to see if the incoming message (i.e. the message from
+V
NOTE: Hardware configuration for a network consisting of 3 or
more MCU’s. Notice that the bus utilizes no more than 1 set of 13K
bias resistors and no more than two 120 termination resistors.
FIGURE 7. HARDWARE CONFIGURATION FOR A NETWORK
MCU
DD
13K
NOTE: Hardware configuration for a network consisting of two
microcomputers. Notice that the pullup resistor is connected to
the BUS- pin and the pulldown to BUS+.
BUS- BUS+
SPI OR SCI
120
SBIC
MCU
OF MICROCOMPUTERS
13K
BUS-
SBIC
BUS+
SPI OR SCI
BUS- BUS+
120
SBIC
MCU
FIGURE 7B.
FIGURE 7A.
13K
13K
BUS- BUS+
SPI OR SCI
BUS-
SBIC
BUS+
SBIC
MCU
BUS- BUS+
SPI OR SCI
SBIC
MCU
MCU