DS1557P-100 DALLAS [Dallas Semiconductor], DS1557P-100 Datasheet - Page 3

• Manufacturer Part Number: DS1557P-100
• Description: 4MEG NV Y2KC Timekeeping RAM
• Manufacturer: DALLAS [Dallas Semiconductor]

DS1557 OPERATING MODES Table 1
DATA READ MODE
The DS1557 is in the read mode whenever
device architecture allows ripple-through access to any valid address location. Valid data will be available
at the DQ pins within t
satisfied. If
access (t
controlled by
intermediate state until t
will remain valid for output data hold time (t
access.
DATA WRITE MODE
The DS1557 is in the write mode whenever
referenced to the latter occurring transition of
the cycle.
read or write cycle. Data in must be valid t
afterward. In a typical application, the
active provided that care is taken with the data bus to avoid bus contention. If
transitioning low, the data bus can become active with read data defined by the address inputs. A low
transition on
DATA RETENTION MODE
The 5-volt device is fully accessible and data can be written and read only when V
However, when V
internal clock registers and SRAM are blocked from any access. When V
point V
battery. RTC operation and SRAM data are maintained from the battery until V
levels.
The 3.3-volt device is fully accessible and data can be written and read only when V
V
power is switched from V
greater than V
V
returned to nominal levels.
All control, data, and address signals must be powered down when V
PF
CC
V
. When V
SO
V
V
drops below V
< V
CC
CC
SO
V
CEA
< V
> V
CC
CC
(battery supply level), device power is switched from the V
CE
) or at output enable access time (t
CE
<V
SO
PF
WE
and
BAT
CC
CE
PF
or
will then disable the outputs t
, the device power is switched from V
falls below V
CC
WE
and
OE
BAT
V
V
V
V
CE
is below the power-fail point V
X
X
AA
. RTC operation and SRAM data are maintained from the battery until V
IH
access times are not met, valid data will be available at the latter of chip enable
IL
IL
IL
must return inactive for a minimum of t
AA
OE
after the last address input is stable, providing that
CC
. If the address inputs are changed while
. If the outputs are activated before t
V
V
OE
to the internal backup lithium battery when V
X
X
X
X
IH
IL
PF
, access to the device is inhibited. If V
WE
V
V
V
X
X
X
IH
IH
IL
OE
DQ0-DQ7
signal will be high during a write cycle. However,
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
CE
D
WE
D
DS
OH
OUT
WEZ
WE
3 of 19
IN
(chip enable) is low and
prior to the end of the write and remain valid for t
) but will then go indeterminate until the next address
OEA
and
after
or
). The state of the data input/output pins (DQ) is
CE
CE
RETENTION
PF
DESELECT
DESELECT
WE
CC
. The addresses must be held valid throughout
are in their active state. The start of a write is
MODE
WRITE
(point at which write protection occurs) the
READ
READ
DATA
to the internal backup lithium battery when
goes active.
WR
prior to the initiation of a subsequent
CE
AA
CC
CC
, the data lines are driven to an
is powered down.
and
pin to the internal backup lithium
CMOS STANDBY
CC
PF
WE
CC
falls below the battery switch
is less than V
OE
STANDBY
BATTERY
CURRENT
CE
POWER
ACTIVE
ACTIVE
ACTIVE
(write enable) is high. The
drops below V
CC
remain valid, output data
and
OE
is returned to nominal
CC
OE
is low prior to
is greater than V
CC
access times are
BAT
is greater than
, the device
PF
OE
. If V
DS1557
can be
CC
PF
WE
DH
PF
is
is
.