DS1557P-100 DALLAS [Dallas Semiconductor], DS1557P-100 Datasheet - Page 7

• Manufacturer Part Number: DS1557P-100
• Description: 4MEG NV Y2KC Timekeeping RAM
• Manufacturer: DALLAS [Dallas Semiconductor]

ALARM MASK BITS Table 3
When the RTC Register values match Alarm Register settings, the Alarm Flag bit (AF) is set to a 1. If
Alarm Flag Enable (AE) is also set to a 1, the alarm condition activates the
signal is cleared by a read or write to the Flags Register (Address 7FF0h) as shown in Figure 2 and 3. The
active, but is not guaranteed to be cleared unless t
write to the Flags Register but the flag will not change states until the end of the read/write cycle and the
CLEARING IRQ WAVEFORMS Figure 2
CLEARING IRQ WAVEFORMS Figure 3
The
occurs and both ABE and AE are set. The ABE and AE bits are cleared during the power-up transition,
however an alarm generated during power-up will set AF. Therefore the AF bit can be read after system
power-up to determine if an alarm was generated during the power-up sequence. Figure 4 illustrates
alarm timing during the battery back-up mode and power-up states.
IRQ
IRQ
AM4
/FT signal may be cleared by having the address stable for as short as 15 ns and either
/FT signal has been cleared.
IRQ
1
1
1
1
0
/FT pin can also be activated in the battery backed mode. The
AM3
1
1
1
0
0
AM2
1
1
0
0
0
AM1
1
0
0
0
0
ALARM RATE
Once per second
When seconds match
When minutes and seconds match
When hours, minutes, and seconds match
When date, hours, minutes, and seconds match
7 of 19
RC
is fulfilled. The alarm flag is also cleared by a read or
IRQ
/FT will go low if an alarm
IRQ
/FT pin. The
CE
IRQ
or
DS1557
WE
/FT