AD7346B AD [Analog Devices], AD7346B Datasheet - Page 3

• Manufacturer Part Number: AD7346B
• Description: 2 Pair/1 Pair ETSI Compatible HDSL Analog Front End
• Manufacturer: AD [Analog Devices]

Parameter
LOGIC OUTPUTS
Output Logic High, V
Output Logic Low, V
POWER SUPPLIES
AVDD, DVDD
IDD
1
2
tones beyong 540 kHz are therefore excluded.
3
4
the receive filter corner frequency. the filter tuning circuit requires a continuous 16.384 MHz clock applied to the Fclk pin.
5
6
7
8
9
Specifications subject to change without notice.
REV PrA
Operating temperature range is as follows: B Version: –40°C to +85°C.
The complete transmit path spectrum and pulse shape comply with ETSI requirements. SNR and THD are measured within a 547 kHz bandwidth. Noise and Spurious
The transmit DAC maximum update rate is half the maximum output data rate i.e. 1168 kHz. The maximum transmit clock is 16 x 1168 = 18.688 MHz.
There are three ranges (bottom range, mid range, top range), each range being divided into eight steps. The transmit filter corner frequency can be set independently from
Transformer turns ratio = 1:2:3 at 50 kHz when loaded by ETSI (RTR/TM3036) HDSL test loops.
With 547 kHz filter snd 0 dB PGA gain selected.
The PGA gain is set by setting the PGA-GC bits in the control register.
The input switching threshold voltage is approximately 1.2 V to allow interfacing to 2.5 V and 3.3 V logic.
The output level is determined by the voltage on the logic supply pin V
Normal Mode (excluding Driver)
Line Driver
OL
OH
9
PRELIMINARY TECHNICAL DATA
AD7346B
Min
VDD - 0.3
3.15
DRIVE
Typ
3.3
32
75
.
– 3 –
Max
0.3
3.45
Units
V
V
V
mA
mA
Test Conditions/Comments
I
I
33 W Differential Load
OUT
OUT
= 200 mA
= 200 mA
AD5011