AD7346B AD [Analog Devices], AD7346B Datasheet - Page 5

• Manufacturer Part Number: AD7346B
• Description: 2 Pair/1 Pair ETSI Compatible HDSL Analog Front End
• Manufacturer: AD [Analog Devices]

REV PrA
The rising edge of TxSYNC can occur anywhere as long at the TxSYNC low time exceeds one TxCLK period. The TxSYNC falling edge
must occur after the TxCLK rising edge which captures the LSB of the previous word. This ensures correct loading into the DAC. The
If R/
which of the four register banks is being written to. The 12 LSBs contain the word. When the AD5011 is reset using RESETB, the
= 1, the selected register's contents will be output on DR. If R/
SCLK activity and serial output data activity does not coincide with the sesitive ADCCLK clock edges
AD C CL K
S CL K
S DO
t
6
PRELIMINARY TECHNICAL DATA
D 11
Figure 2. ADC Timing (1160 kHz < ADCCLK <= 2320 kHz)
t
first 14 bits are loaded into the DAC, the 2 LSBs being don't cares.
9
T xS Y NC
T xD AT A
T xC LK
(R/W = 1)
D 10
t
(R/W = 0
S P ICL K
14
t
8
t
T FS
11
DR
DT
DR
t
17
D 13
R /W SEL2
D 1
t
19
t
13
D 12
Figure 4. Control Interface
D 0
t
t
t
12
18
registers are reset to zero.
7
Figure 3. DAC Timing
SEL1
D 11
t
10
SEL0
t
20
t
15
D 2
D 11
t
D 11
16
– 5 –
D 1
D 10
D 11
D 10
t
21
D 0
D 10
= 0, no data will be output on DR. The SEL bits identify
t
X
D 1
22
D 1
D 1
X
D O
D 0
D 13
D O
t
23
D 12
D 11
D 10
D 9
AD5011