AD7346B AD [Analog Devices], AD7346B Datasheet - Page 4

• Manufacturer Part Number: AD7346B
• Description: 2 Pair/1 Pair ETSI Compatible HDSL Analog Front End
• Manufacturer: AD [Analog Devices]

Parameter
ADCCLK <= 1160kHz
t
t
t
t
t
1160 kHz < ADCCLK <= 2320 kHz
t
t
t
t
t
TRANSMIT DAC
t
t
t
t
t
CONTROL REGISTER
t
t
t
t
t
t
t
t
Guaranteed by design but not production tested.
AD5011
TIMING CHARACTERISTICS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
SCLK activity and serial output data activity does not coincide with the sesitive ADCCLK clock edges
Limit at
T
(B Version)
1.5*t
2*t
2.5*t
3*t
26.939
5
10
20
1*t
1.5*t8
2*t
26.939
5
10
53.5
12
10
t
3
50
76
15
t
15
t
t
7
10
7
10
AD C CL K
11
16
16
16
MIN
S CL K
S DO
3
3
8
8
- 15
- 15
3
3
to T
MAX
t
1
D 11
t
4
Figure 1. ADC Timing (ADCCLK <= 1160 kHz)
D 10
t
3
(V
DD
= +2.7 V to +5.5 V; AGND = DGND = 0 V, unless otherwise noted)
Units
ns min
ns typ
ns min
ns typ
ns min
ns min
ns min
ns min
ns typ
ns min
ns typ
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
t11/2
ns min
ns typ
ns min
ns max
ns min
ns max
ns typ
ns min
ns min
ns min
ns min
D 1
D 0
t
2
t
5
Test Conditions/Comments
ADCCLK Rising Edge to SCLK Rising Edge Delay
SCLK Rising Edge to ADCCLK Falling Edge Delay
SCLK Period (1/32*ADCCLK Period)
Data Setup Time Before SCLK Falling Edge
Data Hold Time After SCLK Falling Edge
ADCCLK Rising Edge to SCLK Rising Edge Delay
SCLK Rising Edge to ADCCLK Falling Edge Delay
SCLK Period (1/16*ADCCLK Period)
Data Setup Time Before SCLK Falling Edge
Data Hold Time After SCLK Falling Edge
TxCLK Period (1/18.688 MHz)
Data Setup Time Before TxCLK Rising Edge
Data Hold Time After TxCLK Rising Edge
TxSYNC Low Time
TxCLK Rising Edge to TxSYNC Falling Edge Delay
ns max
SPICLK Period
TFS Setup Time Before SPICLK Falling Edge
TFS Hold Time After SPICLK Falling Edge
TFS High Time
DT Setup Time Before SPICLK Falling Edge
DT Hold Time After SPICLK Falling Edge
DR Setup Time Before SPICLK Falling Edge (R/
DR Hold Time After SPICLK Falling Edge (R/
– 4 –
D 11
D 10
D 9
= 1)
= 1)
REV PrA