AD9874BST AD [Analog Devices], AD9874BST Datasheet - Page 20

• Manufacturer Part Number: AD9874BST
• Description: IF Digitizing Subsystem
• Manufacturer: AD [Analog Devices]

AD9874
CLOCK SYNTHESIZER
The clock synthesizer is a fully programmable integer-N PLL
capable of 2.2 kHz resolution at clock input frequencies up to
18 MHz and reference frequencies up to 25 MHz. It is similar
to the LO synthesizer described previously in Figure 4 with the
following exceptions:
• It does not include an 8/9 prescaler nor an A counter.
• It includes a negative-resistance core that when used in conjunc-
The 14-bit reference counter and 13-bit N-divider counter can
be programmed via the following registers: CKR and CKN.
The clock frequency, f
frequency by the following equation:
The charge pump current is programmable via the CKI register
from 0.625 mA to 5.0 mA using the following equation:
The fast acquire subcircuit of the charge pump is controlled by
the CKFA Register in the same manner as the LO synthesizer is
controlled by the LOFA Register. An on-chip lock detect function
(enabled by the CKF bit) automatically increases the output
current for faster settling during channel changes. The synthe-
sizer may also be disabled using the CK standby bit located in
the STBY Register.
The AD9874 clock synthesizer circuitry includes a negative-
resistance core so that only an external LC tank circuit with a
varactor is needed to realize a voltage controlled clock oscillator
(VCO). Figure 7a shows the external components required to
complete the clock synthesizer along with the equivalent input
circuitry of the CLK input. The resonant frequency of the VCO
is approximately determined by L
capacitance of C
C
ensure proper locking of the clock synthesizer.
V
f
OSC
CM
VAR
I
tion with an external LC tank and varactor, serves as the VCO.
Figure 7a. External Loop Filter, Varactor, and LC Tank
Are Required to Realize a Complete Clock Synthesizer
f
CLK
PUMP
= VDDC – R
> 1/{2
should be selected to provide a sufficient tuning range to
IOUTC
=
=
(
CKN CKR
(
(L
CKI
BIAS
OSC
R
F
FILTER
LOOP
OSC
C
C
(C
+
I
Z
P
BIAS
VARACTOR
1
AD9874
)
and C
> 1.6V
×
CLK OSC. BIAS
)
R
0 625
CLK
×
D
.
//C
f
VAR
REF
, is related to the reference
OSC
C
C
. As a result, L
mA
OSC
))
VAR
1/2
}
OSC
2
CLKP
and the series equivalent
L
OSC
0.40 mA, OR 0.65 mA
I
OSC
BIAS
VDDC = 3.0 V
R
0.1 F
CLKN
BIAS
, C
= 0.15 mA, 0.25 mA,
OSC
, and
(5)
(6)
–20–
The bias, I
grammable settings. Lower equivalent Q of the LC tank circuit
may require a higher bias setting of the negative-resistance core
to ensure proper oscillation. R
common-mode voltage at CLKP and CLKN is approximately
1.6 V. The synthesizer may be disabled via the CK standby bit
to allow the user to employ an external synthesizer and/or VCO
in place of those resident on the IC. Note, if an external CLK
source or VCO is used, the clock oscillator must be disabled via
the CKO standby bit.
The phase noise performance of the clock synthesizer is depen-
dent on several factors, including the CLK oscillator I
setting, the charge pump setting, the loop filter component
values, and the internal f
how the measured phase noise attributed to the clock synthe-
sizer varies (relative to an external f
I
at 73.35 MHz with an external LO signal at 71.1 MHz. Figure
7b shows that the optimum phase noise is achieved with the
highest I
higher charge pump values provide the optimum performance
for the given loop filter configuration. The AD9874 clock syn-
thesizer and oscillator were set up to provide a f
from an external f
component values were selected for the synthesizer: R
R
1.2 µH, and C
BIAS
D
Figure 7b. CLK Phase Noise vs. I
(CLK SYN Settings: CKI = 7, CLR = 56, and CLN = 60
with f
= 2 kΩ, C
setting and charge pump setting for a –31 dBm IFIN signal
–100
–110
–120
REF
–10
–20
–30
–40
–50
–60
–70
–80
–90
BIAS
0
–25
BIAS
= 100kHz)
(CKO) setting, while Figure 7c shows that the
Z
VAR
, of the negative-resistance core has four pro-
–20
= 0.68 µF, C
CKO = 1
= Toshiba 1SV228 Varactor.
REF
–15
of 16.8 MHz. The following external
CKO = 0
–10
FREQUENCY OFFSET – kHz
REF
P
setting. Figures 7b and 7c show
–5
= 0.1 µF, C
BIAS
0
should be selected so the
CLK
BIAS
5
) as a function of the
CKO = 2
OSC
Setting (CKO)
10
EXT CLK
= 91 pF, L
CLK
15
of 18 MHz
F
20
= 390 Ω,
REV. 0
OSC
BIAS
25
=