AD9874BST AD [Analog Devices], AD9874BST Datasheet - Page 35

• Manufacturer Part Number: AD9874BST
• Description: IF Digitizing Subsystem
• Manufacturer: AD [Analog Devices]

a higher f
first IF’s filtering requirements often depend on the transition
region between the IF frequency and the image band (i.e., ± f
Lastly, the output SSI clock rate, f
strength should be set to their lowest possible settings to mini-
mize the potential harmful effects of digital induced noise while
preserving a reliable data link to the DSP. Note, the SSICRA,
SSICRB, and SSIORD Registers (i.e., 0x18, 0x19, and 0x1A)
provide a large degree of flexibility for optimization of the SSI
interface.
Synchronization of Multiple AD9874s
Some applications such as receiver diversity and beam steering
may require two or more AD9874s operating in parallel while
maintaining synchronization. Figure 28 shows an example of how
multiple AD9874s can be cascaded, with one device serving as
the master and the other devices serving as the slaves. In this
example, all of the devices have the exact same SPI register con-
figuration since they share the same SPI interface to the DSP.
Since the state of each of the AD9874’s internal counters is
unknown upon initialization, synchronization of the devices is
required via a SYNCB pulse (see Figure 4) to synchronize their
digital filters and ensure precise time alignment of the data streams.
Although all of the devices’ synthesizers are enabled, the LO and
CLK signals for the slaves(s) are derived from the masters’ synthe-
sizers and are referenced to an external crystal oscillator. All of
the necessary external components (i.e., loop filters, varactor, LC,
and VCO) to ensure proper closed-loop operation of these
synthesizers are included.
Note, while the VCO output of the LO synthesizer is ac-coupled
to the slave’s LO input(s), all of the CLK inputs of the devices
must be dc-coupled if the AD9874’s CLK oscillators are enabled.
This is due to the dc current required by the CLK oscillators in
each device. In essence, these negative impedance cores are oper-
ating in parallel, increasing the effective Q of the LC resonator
circuit. Note, RBIAS should be sized such that the sum of the
oscillators’ dc bias currents maintains a common-mode voltage
of around 1.6 V.
REV. 0
CLK
is typically more desirable given a choice, since the
CLKOUT
, and digital driver
CLK
/4 ).
–35–
0.1 F
Figure 28. Example of Synchronizing Multiple AD9874s
TO OTHER
AD9874s
R
VDDC
L
BIAS
OSC
C
OSC
VCO
C
R
VAR
D
47
43
42
19
20
19
20
47
42
43
FILTER
CLKP
CLKN
IFIN
LOP
LON
IFIN
LOP
LON
CLKP
CLKN
LOOP
C
C
P
Z
R
F
IOUTL
IOUTC
IOUTC
AD9874
AD9874
MASTER
15
38
FILTER
15
SLAVE
LOOP
CLKOUT
CLKOUT
SYNCB
SYNCB
DOUTA
DOUTA
f
f
REF
REF
PE
PD
PC
PE
PD
PC
FS
FS
23
35
25
24
33
31
29
28
35
31
29
28
25
24
23
33
TO OTHER
AD9874s
AD9874
FROM
CRYSTAL
OSCILLATION
TO
DSP
TO DSP
FROM
DSP