MAX5952 MAXIM [Maxim Integrated Products], MAX5952 Datasheet
MAX5952
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MAX5952 Summary of contents
Page 1
... The MAX5952’s programmability includes start- up timeout, overcurrent timeout, and load-disconnect detection timeout. The MAX5952 is available in a 36-pin SSOP package and is rated for both extended (-40°C to +85°C) and upper commercial (0°C to +85°C) temperature ranges. Power-Sourcing Equipment (PSE) ...
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... SSOP (derate 11.4mW/°C above +70°C) ..........941mW Operating Temperature Ranges: MAX5952_EAX..............…………………………-40°C to +85°C MAX5952_UAX ....................................................0°C to +85°C Storage Temperature Range .............................-65°C to +150°C Junction Temperature ......................................................+150°C Lead Temperature (soldering, 10s) .................................+300°C ...
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ELECTRICAL CHARACTERISTICS (continued) (AGND = 32V to 60V 0V DGND = +3.3V, all voltages are referenced AGND = +48V, DGND = +48V (DGND + 3.3V (Note 2) PARAMETER ...
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... V increasing DD MAX5952A V is set DD_OV DD DGND > decreasing DD_UV DD MAX5952C Device operates when V - DGND > increasing DDUVLO DD Ports shut down and device resets if its junction temperature exceeds this limit, temperature increasing (Note 4) Thermal hysteresis, temperature decreasing (Note AGND, all modes ...
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ELECTRICAL CHARACTERISTICS (continued) (AGND = 32V to 60V 0V DGND = +3.3V, all voltages are referenced AGND = +48V, DGND = +48V (DGND + 3.3V (Note 2) PARAMETER ...
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High-Power, Quad, PSE Controller for Power-Over-Ethernet ELECTRICAL CHARACTERISTICS (continued) (AGND = 32V to 60V 0V DGND = +3.3V, all voltages are referenced AGND = +48V, DGND = +48V (DGND + ...
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ELECTRICAL CHARACTERISTICS (continued) (AGND = 32V to 60V 0V DGND = +3.3V, all voltages are referenced AGND = +48V, DGND = +48V (DGND + 3.3V (Note 2) PARAMETER ...
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High-Power, Quad, PSE Controller for Power-Over-Ethernet = +3.3V, AUTO = AGND = DGND = 0V, RESET = SHD_ = unconnected -48V +25°C, all registers = default setting, unless otherwise noted.) A ANALOG ...
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... TEMPERATURE (°C) OVERCURRENT RESPONSE WAVEFORM = 240Ω TO 57Ω) LOAD MAX5952 toc13 (AGND - V 50V/div 0V I OUT 200mA/div GATE 10V/div INT 2V/div 400μs/div SHORT-CIRCUIT RESPONSE TIME MAX5952 toc15 (AGND - V 20V/div 0V I OUT 10A/div 130mA V GATE_ 10V/div V EE 4μs/div ...
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... MAX5952 toc17 (AGND - V ) OUT 20V/div 0V I OUT 200mA/div 0A V GATE_ 10V/div V EE INT 2V/div 0V 100ms/div STARTUP WITH VALID PD (25kΩ AND 0.1μF) MAX5952 toc19 (AGND - V ) OUT 20V/div I OUT 100mA/div V GATE_ 5V/div 100ms/div MAX5952 toc21 (AGND - V ) OUT 5V/div 0V I OUT 1mA/div 100ms/div ...
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... WITH VALID PD (25kΩ AND 0.1μF) MAX5952 toc23 (AGND - V 20V/div 0V I OUT 100mA/div 0A V 5V/div V EE 100ms/div DETECTION WITH MIDSPAN MODE WITH INVALID PD (33kΩ) MAX5952 toc25 (AGND - V 5V/div 0V I OUT 0A 1mA/div V 10V/div V EE 400ms/div DETECTION WITH INVALID PD (OPEN CIRCUIT, USING TYPICAL OPERATING CIRCUIT 1) MAX5952 toc27 ...
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... I OUT 1mA/div V GATE_ 10V/div FUNCTION DD to set midspan operation. The MIDSPAN value DIG 2 C-compatible system. = 0.5Ω, IVEE = 00, ICUT = 000, SENSE MAX5952 toc29 (AGND - V ) OUT 5V/div CLASS 5 I OUT CLASS 4 20mA/div CLASS 3 CLASS 2 CLASS 1 40ms/div Pin Description with a 50kΩ resistor. ...
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... EE capacitor between AGND and V Auto or Shutdown Mode Input. Force AUTO high to enter auto mode after a reset or power-up. Drive low to put the MAX5952 into shutdown mode. In shutdown mode, software controls the operational modes of 35 AUTO the MAX5952. A 50kΩ internal pulldown resistor defaults to AUTO low. AUTO latches when V ramps up and exceeds its UVLO threshold or when the device resets ...
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... MIDSPAN CENTRAL LOGIC UNIT (CLU) RESET INT DGND V DD AGND ANALOG +10V ANALOG BIAS/ SUPPLY +5V DIG MONITOR VOLTAGE V EE REFERENCES CURRENT REFERENCES MAX5952 14 ______________________________________________________________________________________ OSC_IN DGND VOLTAGE PROBING OSCILLATOR AND MONITOR CURRENT-LIMIT CONTROL DETECTION/ CLASSIFICATION SM ACD_ENABLE PORT STATE MACHINE (SM PWR_EN ...
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... INT output and four independent shutdown inputs (SHD_) provide fast response from a fault to port shut- down between the MAX5952 and the microcontroller. A RESET input allows hardware reset of the device. Reset is a condition the MAX5952 enters after any of the following conditions: 1) After power-up (V UVLO thresholds). ...
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... In auto mode, the MAX5952 performs detection, classi- fication, and powers up the port automatically once a valid PD is detected at the port valid PD is not con- nected at the port, the MAX5952 repeats the detection routine continuously until a valid PD is connected. Going into auto mode, the DET_EN and CLASS_EN bits are set to high and stay high unless changed by soft- ware ...
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... PD detection to the first quadrant as specified by the IEEE 802.3af/at standard. To prevent damage to non-PD devices, and to protect itself from an output short circuit, the MAX5952 limits the current into DET_ to less than 2mA maximum during PD detection. In midspan mode, the MAX5952 waits 2.2s before attempting another detection cycle after every failed detection ...
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... When the MAX5952 enters a powered state, the t and t timers are reset. Before turning on the port DISC power, the MAX5952 checks if any other port is not turning on and if the t timer is zero. Another FAULT check is performed if the ACD_EN bit is set, in this case the OSC_FAIL bit must be low (oscillator is okay) for the port to be powered ...
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... MAX5952 sets the IVC bit in register R09h. The ICUT register determines the maximum current lim- its allowed for each port of the MAX5952. The 3 ICUT bits (R2Ah[6:4], R2Ah[2:0], R2Bh[6:4], and R2Bh[2:0]) allow programming of the current-limit and overcurrent thresholds in excess of the IEEE standard limit (see ...
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... C GD DRAIN of the external MOSFET. Current limit and the capacitive load at the drain control the slew rate during LIM startup. During current-limit regulation, the MAX5952 manipulates the GATE_ voltage to control the voltage > OUT EE ...
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... The MAX5952 also features +2.0V DDUVLO DDUVLO MAX5952 in reset and the ports shut off. Bit 0 in the supply event register shows the status of V (Table 12) after V has recovered. All logic inputs and DD outputs reference to DGND. DGND and AGND must be connected together externally ...
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... MAX5952 SDAOUT operates as an open-drain output pullup resistor, typically 4.7kΩ, is required on SDAOUT. The MAX5952 SCL line operates only as an input. A pullup resistor, typically 4.7kΩ, is required on SCL if there are multiple masters the master in a single- master system has an open-drain SCL output. t SU, STA ...
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... Each transmission consists of a START condition (Figure 6) sent by a master, followed by the MAX5952 7-bit slave address plus R/W bit, a register address byte, one or more data bytes, and finally a STOP condition. START and STOP Conditions Both SCL and SDA remain high when the interface is not busy ...
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... A1, and A0 represent the states of the MAX5952’s A3, A2, A1, and A0 inputs, allowing up to sixteen MAX5952 devices to share the bus. The states of the A3, A2, A1 and A0 latch in upon the reset of the MAX5952 into reg- ister R11h. The MAX5952 monitors the bus continuous- ly, waiting for a START condition followed by the MAX5952’ ...
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... Thus, a read is initiated by first configuring the MAX5952’s command byte by performing a write (Figure 11). The master now reads ‘n’ consecutive bytes from the MAX5952, with the first data byte read from the regis- ter addressed by the initialized command byte (Figure 12). When performing read-after-write verification, remember to reset the command byte’ ...
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High-Power, Quad, PSE Controller for Power-Over-Ethernet Register Map and Description The interrupt register (Table 6) summarizes the event register status and is used to send an interrupt signal (INT goes low) to the controller. Writing R1Ah[7] clears ...
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The power event register (Table 8) records changes in the power status of the four ports. Any change in PGOOD_ (R10h[7:4]) sets PG_CHG_ to 1. Any change in the PWR_EN_ (R10h[3:0]) sets PWEN_CHG_ to 1. PG_CHG_ and PWEN_CHG_ trigger on ...
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High-Power, Quad, PSE Controller for Power-Over-Ethernet LD_DISC_ is set high whenever the corresponding port shuts down due to detection of load removal. IMAX_FLT_ is set high when the port shuts down due to an extended overcurrent event after a successful ...
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... V 0 DD_UVLO ______________________________________________________________________________________ High-Power, Quad, PSE Controller for Power-Over-Ethernet When V MAX5952 is in reset mode and securely holds all ports is set to 1 whenev- off. When V UVLO thresholds, the device comes out of reset as /V falls soon as the last supply crosses the UVLO threshold. ...
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... CLASS_[2:0] bits are set to 000 and the classifi- cation result is reported in locations R2Ch–R2Fh protection, when POFF_CL (R17h[3], Table 18) is set to 1, the MAX5952 prohibits turning on power to the port that returns a status 111 after classification. A reset sets 0Ch, 0Dh, 0Eh, and 0Fh = 00h. ...
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... PGOOD1 4 PWR_EN4 3 PWR_EN3 2 PWR_EN2 1 PWR_EN1 0 A3, A2, A1, A0 (Table 15) represent the four LSBs of the MAX5952 address (Table 4). During a reset, the device latches into R11h. These four bits address from Table 15. Address Input Status Register ADDRESS = 11h SYMBOL BIT Reserved 7 Reserved ...
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... High-Power, Quad, PSE Controller for Power-Over-Ethernet The MAX5952 uses two bits for each port to set the mode of operation. Set the modes according to Table 16. A reset sets R12h = AAAAAAAA where A represents the latched-in state of the AUTO input prior to the reset. Table 16. Mode Register ...
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Setting DET_EN_/CLASS_EN_ to 1 (Table 18) enables load detection/classification, respectively. Detection always has priority over classification. To perform clas- sification without detection, set the DET_EN_ bit low and CLASS_EN_ bit high. In manual mode, R14h works like a pushbutton. Set ...
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... Set the bits in R16h to scale the TSTART, TFAULT, and TDISC to a multiple of their nominal value specified in the Electrical Characteristics table. When the MAX5952 shuts down a port due to an extended overcurrent condition (either during startup or normal operation), if RSRT_EN is set high, the part does not allow the port to power back on before the restart timer (Table 20b) returns to zero ...
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... After execution, the bits reset to 0. During detection or classification, if PWR_ON_ goes high, the MAX5952 gracefully terminates the current operation and turns on power to the port. The MAX5952 ignores the PWR_ON_ in auto mode. A reset sets R19h = 00h. A logic-high powers off port 4 ...
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... W RESET_P4 3 W RESET_P3 2 W RESET_P2 1 W RESET_P1 0 W The ID register (Table 24) keeps track of the device ID number and revision. The MAX5952’s ID_CODE[4:0] = 11000b. Contact the factory for REV[2:0] value. Table 24. ID Register ADDRESS = 1Bh SYMBOL BIT R ID_CODE ...
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... While in hardware-controlled mode, the MAX5952 ignores all requests to turn the power on and the flag SMODE_ indicates that the hardware has taken control of the MAX5952 operation. In addition, the software is not allowed to change the mode of operation in hard- ware-controlled mode. A reset sets R1Eh = 00h. ...
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... The CLC_EN enables the large capacitor detection fea- ture. When CLC_EN is set the device can recognize a capacitor load up to 100µF. If the CLC_EN is reset, the MAX5952 performs normal detection. AC_TH allows programming of the threshold of the AC disconnect comparator. The threshold is defined as a current since the comparators verify that the peak of the current pulses sensed at the DET_ input exceed a preset threshold ...
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Table 29. High-Power Mode Register ADDRESS = 24h SYMBOL BIT R/W 7 — 3 — Reserved 2 — 1 — 0 — Table 30. Reserved ADDRESS = 25h SYMBOL BIT R/W 7 — 6 — 5 — 4 — Reserved ...
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... The three ICUT_ bits (Tables 34a and 34b) allow pro- gramming of the current-limit and overcurrent thresholds in excess of the IEEE 802.3af standard limit. The MAX5952 can automatically set the ICUT register or can be manually written to by the software (see Table 3). Table 34a. ICUT Registers 1 and 2 ...
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... Reserved 6 — The MAX5952 provides current readout for each port during classification and normal power mode. The cur- rent per port information is separated into 9 bits. They are organized into 2 consecutive registers for each one of the ports. The information can be quickly retrieved using the auto-increment option of the address pointer ...
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High-Power, Quad, PSE Controller for Power-Over-Ethernet Table 37. Register Summary ADDR REGISTER NAME R/W PORT BIT 7 INTERRUPTS 00h Interrupt RO G SUP_FLT 01h Int Mask R/W G MASK7 EVENTS 02h Power Event RO 4321 PG_CHG4 03h Power Event CoR ...
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Table 37. Register Summary (continued) ADDR REGISTER NAME R/W PORT MAXIM RESERVED 20H Reserved G Reserved 21H Reserved G Reserved 22H Reserved G Reserved 23H Program 1 R/W 4321 Reserved 24h High Power Mode R/W G Reserved 25h Reserved — ...
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... TD1+* 19 TX1- 5 TD1- -48VOUT 0.1μF 75Ω 23 RXT1 1000pF 250VAC 0.1μF 75Ω 20 TXCT1 -48VRTN V DD 3kΩ SDAOUT 3kΩ SDAIN MAX5952 HPCL063L 3kΩ SCL HPCL063L DGND 0.5Ω 1% -48V 1N4002 FDT3612 100V, 120mΩ SOT-223 CHANNELS Applications Information RJ–45 CONNECTOR 0.1μF 75Ω ...
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... OPTIONAL BUFFER 180Ω SCL OPTIONAL BUFFER Figure 14. PoE System Block Diagram ______________________________________________________________________________________ High-Power, Quad, PSE Controller for Power-Over-Ethernet -48VRTN V DD 3kΩ SDAOUT 3kΩ SDAIN MAX5952 HPCL063L 3kΩ SCL HPCL063L DGND 0.5Ω 1% -48V 1N4002 FDT3612 100V, 120mΩ SOT-223 CHANNELS RJ–45 ...
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High-Power, Quad, PSE Controller for Power-Over-Ethernet R10 2Ω R6 1Ω C3 15nF Q4 MMBTA56 GND GND 1 MAX5020 0.47μF 4 100V SS_SHDN C2 0.022μF -48V -48V Figure 15. -48V to +3.3V (300mA) Boost ...
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... DET4 14 DGND SHD1 17 SHD2 18 SSOP ______________________________________________________________________________________ for Power-Over-Ethernet Component List for V DESIGNATION Q1 Q2, Q3 R4, R6 R10 U1 PART MAX5952A_ 36 OSC MAX5952C_ 35 AUTO 34 OUT1 33 GATE1 32 SENSE1 31 OUT2 30 GATE2 29 SENSE2 OUT3 26 GATE3 25 SENSE3 24 OUT4 23 GATE4 22 SENSE4 21 AGND ...
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... NOTE: ALL SIGNAL PINS ARE REFERENCED TO DGND. DGND RANGE IS BETWEEN V Typical Operating Circuit 1 (without AC Load Removal Detection) 48 ______________________________________________________________________________________ -48VRTN 1.8V TO 3.7V, (REF TO DGND 3kΩ SDAOUT 3kΩ SDAIN MAX5952 HPCL063L 3kΩ SCL HPCL063L DGND 0.5Ω 1% -48V AND (AGND + 4V). EE Typical Operating Circuits -48V RTN OUTPUT TO PORT V 1kΩ ...
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... Typical Operating Circuit 2 (with AC Load Removal Detection) ______________________________________________________________________________________ High-Power, Quad, PSE Controller for Power-Over-Ethernet Typical Operating Circuits (continued) -48VRTN 1.8V TO 3.7V 3kΩ SDAOUT 3kΩ SDAIN MAX5952 HPCL063L 3kΩ SCL HPCL063L DGND 0.5Ω 1% -48V CHANNELS PROCESS: BiCMOS -48V RTN OUTPUT TO PORT ...
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High-Power, Quad, PSE Controller for Power-Over-Ethernet (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages TOP VIEW FRONT VIEW Maxim cannot ...