MAX5952 MAXIM [Maxim Integrated Products], MAX5952 Datasheet - Page 18

• Manufacturer Part Number: MAX5952
• Description: High-Power, Quad, PSE Controller for Power-Over-Ethernet
• Manufacturer: MAXIM [Maxim Integrated Products]

High-Power, Quad, PSE Controller
for Power-Over-Ethernet
During the PD classification mode, the MAX5952 forces
a probe voltage (-18V) at DET_ and measures the cur-
rent into DET_. The measured current determines the
class of the PD.
After each classification cycle, the device sets the
CL_END_ bit (R04h/05h[7:4]) high and reports the clas-
sification results in the status registers R0Ch[6:4],
R0Dh[6:4], R0Eh[6:4], and R0Fh[6:4]. The CL_END_ bit
is reset to low when read through register R05h or after
a port reset. Both status registers, R04h, and R05h are
cleared after the port powers down. Table 2 shows the
IEEE 802.3af requirement for a PSE classifying a PD at
the power interface (PI).
The MAX5952 supports high power beyond the IEEE
802.3af standard by providing additional classifications
(Class 5 and ping-pong classification).
When the MAX5952 enters a powered state, the t
and t
power, the MAX5952 checks if any other port is not
turning on and if the t
check is performed if the ACD_EN bit is set, in this
case the OSC_FAIL bit must be low (oscillator is okay)
for the port to be powered.
Table 2. PSE Classification of a PD (Table
33.4 of the IEEE 802.3af)
18
MEASURED I
______________________________________________________________________________________
DISC
> 13 and < 16
> 21 and < 25
> 31 and < 35
> 45 and < 51
> 5 and < 8
16 to 21
25 to 31
35 to 45
51 to 68
8 to 13
0 to 5
timers are reset. Before turning on the port
CLASS
Powered Device Classification
(mA)
FAULT
Class 0
May be Class 0 and 1
Class 1
May be Class 1 or 2
Class 2
May be Class 2 or 3
Class 3
May be Class 3 or 4
Class 4
May be Class 4 or 5
Class 5
(PD Classification)
timer is zero. Another
CLASSIFICATION
Powered State
START
If these conditions are met, the MAX5952 enters startup
where it turns on power to the port. An internal signal,
POK_, asserts high when V
PGOOD_ status bits are set high if POK_ stays high
longer than t
POK goes low.
The PWR_CHG bit sets when a port powers up or
down. PWR_EN sets when a port powers up and resets
when a port shuts down. The port shutdown timer lasts
0.5ms and prevents other ports from turning off during
that period, except in the case of emergency shut-
downs (RESET = L, RESET_IC = H, V
and TSHD).
The MAX5952 always checks the status of all ports before
turning off. A priority logic system determines the order to
prevent the simultaneous turn-on or turn-off of the ports.
The port with the lesser ordinal number gets priority over
the others (i.e., port 1 turns on first, port 2 second, port 3
third and port 4 fourth). Setting PWR_OFF_ high turns off
power to the corresponding port.
Figure 1. Detection, Classification, and Power-Up Port
Sequence
OUT_
-18V
-48V
-4V
-9V
0V
0V
80ms
PGOOD
150ms
t
DETI
. PGOOD immediately resets when
OUT
150ms
t
DETII
is within 2V from V
EEUVLO,
21.3ms
t
CLASS
V
DDUVLO,
EE
t
.