HI3-574ALN-5 INTERSIL [Intersil Corporation], HI3-574ALN-5 Datasheet - Page 12

• Manufacturer Part Number: HI3-574ALN-5
• Description: Complete, 12-Bit A/D Converters with Microprocessor Interface
• Manufacturer: INTERSIL [Intersil Corporation]

HI-774
The device driving the HI-774 analog input will see a nominal
load of 5k
other end of these input resistors may change as much as
are caused by the internal DAC changing codes which
causes a glitch on the summing junction. This creates abrupt
changes in current at the analog input causing a “kick back”
glitch from the input. Because the algorithm starts with the
MSB, the first glitches will be the largest and get smaller as
the conversion proceeds. These glitches can occur at 350ns
intervals so an op amp with a low output impedance and fast
settling is desirable. Ultimately the input must settle to within
the window of Figure 1 at the bit decision points in order to
achieve 12-bit accuracy.
The HI-774 differs from the most high-speed successive
approximation type ADC’s in that it does not require a high
performance buffer or sample and hold. With error correction
the input can settle while the conversion is underway, but
only during the first 4.8 s. The input must be within 10.76%
of the final value when the MSB decision is made. This
occurs approximately 650ns after the conversion has been
initiated. Digital error correction also loosens the bandwidth
requirements of the buffer or sample and hold. As long as
the input “kick back” disturbances settle within the window of
Figure 1 the device will remain accurate. The combined
effect of settling and the “kick back” disturbances must
remain in the Figure 1 window.
If the design is being optimized for speed, the input device
should have closed loop bandwidth to 3MHz, and a low out-
put impedance (calculated by dividing the open loop output
resistance by the open loop gain). If the application requires
a high speed sample and hold the Intersil HA-5330 or
HA-5320 are recommended.
In any design the input (pin 13 or 14) should be checked
during a conversion to make sure that the input stays within
the correctable window of Figure 1.
Digital Error Correction
HI-774
The HI-774 features the smart successive approximation
register (SSAR) which includes digital error correction. This
has the advantage of allowing the initial input to vary within a
+31 to -32 LSB window about the final value. The input can
move during the first 4.8 s, after which it must remain stable
within
before the input has settled completely; however, it must be
within the window as described in Figure 1.
The conversion cycle starts by making the first 8-bit decisions
very quickly, allowing the internal DAC to settle only to 8-bit
accuracy. Then the converter goes through two error correc-
tion cycles. At this point the input must be stable within
LSB. These cycles correct the 8-bit word to 12-bit accuracy for
any errors made (up to +16 or -32 LSBs). This is up one count
or down two counts at 8-bit resolution. The converter then
continues to make the 4 LSB decisions, settling out to 12-bit
accuracy. The last four bits can adjust the code in the positive
400mV with each bit decision. These input disturbances
1
/
2
LSB. With this feature a conversion can start
(10V range) or 10k
(20V range). However, the
HI-574A, HI-674A, HI-774
1
/
6-963
2
direction by up to 15 LSBs. This results in a total correction
range of +31 to -32 LSBs. When an 8-bit conversion is per-
formed, the input must settle to within
tion (which equals 8 LSBs at 12-bit resolution).
With the HI-774 a conversion can be initiated before the
input has completely settled, as long as it meets the con-
straints of the Figure 1 window. This allows the user to start
conversion up to 4.8 s earlier than with a typical analog to
digital converter. A typical successive approximation type
ADC must have a constant input during a conversion
because once a bit decision is made it is locked in and can-
not change.
†
-15V
When driving the 20V (pin 14) input, minimize capacitance on pin 13.
FIGURE 1. HI-774 ERROR CORRECTION WINDOW vs TIME
CONVERSION
ANALOG
INITIATED
INPUTS
100
-16
-31
32
16
-8
8
0
100K
0V TO +10V
0V TO +20V
OFFSET
100K
BIT DECISION POINTS
R1
FIGURE 2. UNIPOLAR CONNECTIONS
MSB BIT DECISION
~
1
650ns
R2
2
+15V
100
GAIN
3
TIME ( s)
4
2 12/8
3 CS
4 A
5 R/C
6 CE
10 REF IN
8 REF OUT
12 BIP OFF
13 10V
14 20V
9 ANA
COM
12-BIT CONVERSION
8-BIT CONVERSION
5
O
IN
IN
~
1
6
†
/
4.8 s
2
MIDDLE BITS
LSB at 8-bit resolu-
DIG COM 15
DECISION
1
LAST BIT
(12-BIT)
HIGH BITS
/
LOW BITS
2
7
LSB
+15V 7
-15V 11
STS 28
+5V 1
24-27
20-23
16-19
CONVERSION
8
END OF
(12 BIT)