HI3-574ALN-5 INTERSIL [Intersil Corporation], HI3-574ALN-5 Datasheet - Page 14

• Manufacturer Part Number: HI3-574ALN-5
• Description: Complete, 12-Bit A/D Converters with Microprocessor Interface
• Manufacturer: INTERSIL [Intersil Corporation]

“Stand-Alone Operation”
The simplest control interface calls for a singe control line
connected to R/C. Also, CE and 12/8 are wired high, CS and
A
12 bits each.
The R/C signal may have any duty cycle within (and
including) the extremes shown in Figures 8 and 9. In gen-
eral, data may be read when R/C is high unless STS is also
high, indicating a conversion is in progress. Timing parame-
ters particular to this mode of operation are listed below
under “Stand-Alone Mode Timing”.
Time is measured from 50% level of digital transitions. Tested with a
50pF and 3k load.
Time is measured from 50% level of digital transitions. Tested with a
50pF and 3k load.
SYMBOL
SYMBOL
SYMBOL
O
t
t
t
t
t
t
t
t
t
t
t
t
HDR
HRH
DDR
HDR
HRH
DDR
HDR
HRH
DDR
HRL
t
t
HRL
t
t
HRL
t
t
are wired low, and the output data appears in words of
DS
HS
DS
HS
DS
HS
Low R/C Pulse Width
STS Delay from R/C
Data Valid after R/C Low
STS Delay after Data Valid 300
High R/C Pulse Width
Data Access Time
Low R/C Pulse Width
STS Delay from R/C
Data Valid after R/C Low
STS Delay after Data Valid
High R/C Pulse Width
Data Access Time
Low R/C Pulse Width
STS Delay from R/C
Data Valid after R/C Low
STS Delay after Data Valid
High R/C Pulse Width
Data Access Time
HI-574A STAND-ALONE MODE TIMING
HI-674A STAND-ALONE MODE TIMING
HI-774 STAND-ALONE MODE TIMING
PARAMETER
PARAMETER
PARAMETER
MIN
MIN
MIN
150
150
150
50
25
50
25
25
50
20
-
-
-
-
-
-
-
TYP
TYP
TYP
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
HI-574A, HI-674A, HI-774
MAX UNITS
1200
MAX UNITS
MAX UNITS
200
150
200
850
150
200
850
150
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6-965
Conversion Length
A Convert Start transition (see Table 1) latches the state of
A
12 bits (A
read following an 8-bit conversion, the last three LSBs will
read ZERO and DB3 will read ONE. A
is also involved in enabling the output buffers (see “Reading
the Output Data”). No other control inputs are latched.
Conversion Start
A conversion may be initiated as shown in Table 1 by a logic
transition on any of three inputs: CE, CS or R/C. The last of
the three to reach the correct state starts the conversion, so
one, two or all three may be dynamically controlled. The
nominal delay from each is the same, and if necessary, all
three may change state simultaneously. However, to ensure
that a particular input controls the start of conversion, the
other two should be set up at least 50ns earlier. See the
HI-774 Timing Specifications, Convert Mode.
This variety of HI-X74(A) control modes allows a simple
interface in most system applications. The Convert Start
timing relationships are illustrated in Figure 4.
The output signal STS indicates status of the converter by
going high only while a conversion is in progress. While STS
is high, the output buffers remain in a high impedance state
and data cannot be read. Also, an additional Start Convert
will not reset the converter or reinitiate a conversion while
STS is high.
Reading the Output Data
The output data buffers remain in a high impedance state
until four conditions are met: R/C high, STS low, CE high and
CS low. At that time, data lines become active according to
the state of inputs 12/8 and A
illustrated in Figure 5.
O
TABLE 1. TRUTH TABLE FOR HI-X74(A) CONTROL INPUTS
CE
X
0
1
1
1
1
1
1
1
, which determines whether the conversion continues for
CS
X
1
0
0
0
0
0
0
0
O
low) or stops with 8 bits (A
R/C
X
X
0
0
0
0
1
1
1
12/8
X
X
X
X
X
X
X
X
1
0
0
A
X
X
0
1
0
1
0
1
X
0
1
O
None
None
Initiate 12-bit conversion
Initiate 8-bit conversion
Initiate 12-bit conversion
Initiate 8-bit conversion
Initiate 12-bit conversion
Initiate 8-bit conversion
Enable 12-bit Output
Enable 8 MSBs Only
Enable 4 LSBs Plus 4 Trailing
Zeroes
O
. Timing constraints are
O
O
high). If all 12 bits are
OPERATION
is latched because it