HI3-574ALN-5 INTERSIL [Intersil Corporation], HI3-574ALN-5 Datasheet - Page 15

• Manufacturer Part Number: HI3-574ALN-5
• Description: Complete, 12-Bit A/D Converters with Microprocessor Interface
• Manufacturer: INTERSIL [Intersil Corporation]

The 12/8 input will be tied high or low in most applications,
though it is fully TTL/CMOS-compatible. With 12/8 high, all
12 output lines become active simultaneously, for interface to
a 12-bit or 16-bit data bus. The A
With 12/8 low, the output is organized in two 8-bit bytes,
selected one at a time by A
to be connected as shown in Figure 6. A
the least significant bit of the address bus, for storing the
HI-X74(A) output in two consecutive memory locations.
(With A
MSBs are disabled, bits 4 through 7 are forced low, and the 4
LSBs are enabled). This two byte format is considered “left
justified data,” for which a decimal (or binary!) point is
assumed to the left of byte 1:
Further, A
the converter. Break-before-make action is guaranteed
between the two data bytes, which assures that the outputs
strapped together in Figure 6 will never be enabled at the
same time.
A read operation usually begins after the conversion is
complete and STS is low. For earliest access to the data,
however, the read should begin no later than (t
before STS goes low. See Figure 5.
DB11-DB0
MSB
X
STS
R/C
See HI-774 Timing Specifications for more information.
X
CE
CS
A
O
O
low, the 8 MSBs only are enabled. With A
X
O
t
t
BYTE 1
t
SSC
SRC
may be toggled at any time without damage to
FIGURE 4. CONVERT START TIMING
SAC
X
t
HRC
t
HAC
X
t
DSC
X
X
HIGH IMPEDANCE
X
O
. This allows an 8-bit data bus
X
O
t
t
HEC
HSC
input is ignored.
X
X
t
O
C
LSB
BYTE 2
X
is usually tied to
HI-574A, HI-674A, HI-774
0
DD
0
O
high, 4
+ t
0
HS
0
6-966
)
DB11-DB0
A
STS
R/C
See HI-774 Timing Specifications for more information.
O
CE
CS
A
FIGURE 6. INTERFACE TO AN 8-BIT DATA BUS
O
10
11
12
13
14
1
2
3
4
5
6
7
8
9
FIGURE 5. READ CYCLE TIMING
12/8
A
O
ADDRESS BUS
HI-774
DB11 (MSB)
DB0 (LSB)
HIGH IMPEDANCE
COM.
DIG.
t
t
t
STS
SSR
SRR
SAR
t
DD
t
HS
28
27
26
25
24
23
22
21
20
19
18
17
16
15
t
t
t
HSR
HRR
HAR
VALID
DATA
t
HL
t
HD
DATA
BUS