MAX6884ETP MAXIM [Maxim Integrated Products], MAX6884ETP Datasheet - Page 26

• Manufacturer Part Number: MAX6884ETP
• Description: EEPROM-Programmable, Hex Power-Supply Supervisory Circuits
• Manufacturer: MAXIM [Maxim Integrated Products]

EEPROM-Programmable, Hex
Power-Supply Supervisory Circuits
The MAX6884/MAX6885 feature an I
ble 2-wire serial interface consisting of a serial data line
(SDA) and a serial clock line (SCL). SDA and SCL facili-
tate bidirectional communication between the
MAX6884/MAX6885 and the master device at clock
rates up to 400kHz.
timing diagram. The MAX6884/MAX6885 are transmit/
receive slave-only devices, relying upon a master
device to generate a clock signal. The master device
(typically a microcontroller) initiates data transfer on the
bus and generates SCL to permit that transfer.
A master device communicates to the MAX6884/
MAX6885 by transmitting the proper address followed by
command and/or data words. Each transmit sequence is
Figure
Figure
26
t
HD:STA
SDA
SCL
SDA
SCL
______________________________________________________________________________________
CONDITION
6. Serial Interface Timing
7. Bit Transfer
START
DATA LINE STABLE,
DATA VALID
t
SU:DAT
SMBus/I
t
LOW
Figure
DATA ALLOWED
CHANGE OF
t
R
2
C-Compatible Serial Interface
t
HIGH
6 shows the 2-wire interface
t
F
2
C/SMBus-compati-
t
HD:DAT
t
SU:STA
REPEATED START
CONDITION
framed by a START (S) or REPEATED START (SR) condi-
tion and a STOP (P) condition. Each word transmitted
over the bus is 8 bits long and is always followed by an
acknowledge pulse.
SCL is a logic input, while SDA is an open-drain
input/output. SCL and SDA both require external pullup
resistors to generate the logic-high voltage. Use 4.7kΩ
resistors for most applications.
Each clock pulse transfers one data bit. The data on
SDA must remain stable while SCL is high (see
7), otherwise the MAX6884/MAX6885 register a START
or STOP condition (see
and SCL idle high when the bus is not busy.
Figure
SDA
SCL
CONDITION
START
8. Start and Stop Conditions
t
S
HD:STA
Figure
t
SU:STO
8) from the master. SDA
CONDITION
STOP
t
BUF
Bit Transfer
CONDITION
START
CONDITION
STOP
Figure
P