MAX6909 MAXIM [Maxim Integrated Products], MAX6909 Datasheet - Page 20

• Manufacturer Part Number: MAX6909
• Description: I2C-Compatible Real-Time Clocks with uP Supervisor and NV RAM Controller
• Manufacturer: MAXIM [Maxim Integrated Products]

The alarm function generates an ALARM when the con-
tents of the SEC, MIN, HR, DATE, MONTH, DAY, or
YEAR registers match the respective alarm threshold
registers. Also, the generation of the ALARM is pro-
grammable through the alarm configuration register.
The alarm configuration register can be written to with
an address of 94H or it can be read with an address of
95H. The alarm configuration register definition is
shown in Figure 5 (register address definition). Placing
a 1 in the appropriate bit enables the ALM and the
alarm out status bit when the selected alarm threshold
register contents match the respective timekeeping
register contents. For example, writing 0000 0001 to the
alarm configuration register causes the alarm pin to get
triggered every minute (each time the contents of the
seconds timekeeping register match the contents of the
seconds alarm threshold register). Writing 0000 0010
causes the alarm to go on every hour (each time the
contents of the minutes timekeeping register match the
contents of the minutes alarm threshold register).
Writing a 0100 1111 to the alarm configuration register,
therefore, causes the alarm to be triggered on a specif-
ic second, of a specific minute, of a specific hour, of a
specific date, of a specific year. The alarm output stays
low until it is “cleared” by reading or writing to the alarm
configuration register or by reading or writing to any of
the alarm threshold registers.
An alarm out status bit is available if it is desired to use
the alarm function as a polled alarm instead of connect-
ing directly to the ALM output pin. Bit D7 in the minutes
timekeeping register contains the status of the ALM
output with a 1 indicating the alarm function has trig-
gered and zero indicating no triggered alarm.
Many microprocessor-based products require manual-
reset capability, allowing the operator, a test techni-
cian, or external logic circuitry to initiate a reset. With
the MAX6909/MAX6910, a logic low on MR asserts
reset. Reset remains asserted while MR is low, and for
t
pullup resistor of typically 50kΩ, so it can be left open if
it is not used. Internal debounce circuitry requires a
minimum low time on the MR input of 1µs with 100ns
(typ) minimum glitch immunity.
I
Supervisor and NV RAM Controller
20
RP
2
(Figure 7) after it returns high. MR has an internal
C-Compatible Real-Time Clocks with µP
______________________________________________________________________________________
Minutes Register (Alarm Out Status)
Alarm Generation Registers
Manual Reset Input
A µP’s reset input starts the µP in a known state. When
RESET and RESET are active, all control inputs (MR,
WDI, CE IN, and the 2-wire interface) are disabled. The
MAX6909/MAX6910 µP supervisory circuit asserts a
reset to prevent code-execution errors during power-up,
power-down, and brownout conditions. RESET, open-
drain active low, and RESET (push-pull active high) are
guaranteed to be active for 0V < V
V
threshold, an internal timer keeps RESET and RESET
active for the reset timeout period (t
RESET becomes inactive (high) and RESET becomes
inactive (low). If a brownout condition occurs (V
below the reset threshold), RESET and RESET become
active. Each time RESET and RESET are asserted, they
are held active for the reset timeout period.
The MAX69_ _EO30 is optimized to monitor 3.0V ±10%
power supplies. Except when MR is asserted, reset
does not occur until V
but is guaranteed to occur before the power supply
falls below +2.5V.
The MAX69_ _EO33 is optimized to monitor 3.3V ±10%
power supplies. Except when MR is asserted, reset
does not occur until V
above 3.3V - 10%), but is guaranteed to occur before
the power supply falls below 2.8V.
See the Maximum Transient Duration vs. Reset
Comparator Overdrive graph in the Typical Operating
Characteristics.
Figure 7. Manual Reset Timing
OUT
RESET
V
MR
CC
is greater than 1V. Once V
V
RST
t
RP
CC
CC
falls below 2.7V (3.0V - 10%),
falls below 3.0V (3.0V is just
CC
RP
CC
Reset Outputs
); after this interval,
exceeds the reset
< V
RST
, provided
CC
t
dips
RP