MAX6909 MAXIM [Maxim Integrated Products], MAX6909 Datasheet - Page 27

• Manufacturer Part Number: MAX6909
• Description: I2C-Compatible Real-Time Clocks with uP Supervisor and NV RAM Controller
• Manufacturer: MAXIM [Maxim Integrated Products]

Both SDA and SCL remain high when the bus is not
busy. A high-to-low transition of SDA, while SCL is high,
is defined as the START (S) condition. A low-to-high
transition of the data line while SCL is high is defined as
the STOP (P) condition (Figure 22).
The number of data bytes between the START and
STOP conditions for the transmitter and receiver are
unlimited. Each 8-bit byte is followed by an acknowl-
edge bit. The acknowledge bit is a high-level signal put
on SDA by the transmitter, during which time the mas-
ter generates an extra acknowledge-related clock
pulse. A slave receiver that is addressed must gener-
ate an acknowledge after each byte it receives. Also, a
master receiver must generate an acknowledge after
each byte it receives that has been clocked out of the
slave transmitter.
The device that acknowledges must pull down the SDA
line during the acknowledge clock pulse, so that the
SDA line is stable low during the high period of the
acknowledge clock pulse (setup and hold times must
also be met). A master receiver must signal an end of
the data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out
of the slave. In this case, the transmitter must leave SDA
high to enable the master to generate a STOP condition.
Before any data is transmitted on the bus, the device that
should respond is addressed first. The first byte sent after
the start (S) procedure is the address byte. The
MAX6909/MAX6910 act as a slave transmitter/receiver.
Therefore, SCL is only an input clock signal and SDA is a
bidirectional data line. The slave address for the
MAX6909/MAX6910 is shown in Figure 23.
Figure 23. MAX6909/MAX6910 2-Wire Slave Address Byte
Figure 24. Address/Command Byte
BIT 7
1
7
1
RAM
1
6
/CLK
I
2
A5
0
5
______________________________________________________________________________________
START and STOP Conditions
C-Compatible Real-Time Clocks with µP
A4
1
4
A3
Slave Address Byte
0
3
Supervisor and NV RAM Controller
A2
0
2
Acknowledge
A1
0
1
RD
RD/W
BIT 0
0
/W
The command byte is shown in Figure 24. The MSB (bit 7)
must be a logic 1. If it is zero, writes to the MAX6909/
MAX6910 are disabled. Bit 6 specifies clock/calendar
data if logic 0 or RAM data if logic 1. Bits 1 through 5
specify the designated registers to be input or output, and
the LSB (bit 0) specifies a write operation (input) if logic 0
or a read operation (output) if logic 1. The command byte
is always input starting with the MSB (bit 7).
The timekeeping registers (seconds, minutes, hours,
date, month, day, and year) can be read either with a
single read or a burst read. The century register can
only be read with a single read. Since the real-time
clock runs continuously and a read takes a finite
amount of time, there is the possibility that the clock
counters could change during a read operation, there-
by reporting inaccurate timekeeping data. In the
MAX6909/MAX6910, each clock register’s data is
buffered by a latch. Clock register data is latched by
the 2-wire bus read command (on the falling edge of
SCL when the slave acknowledge bit is sent after the
address/command byte has been sent by the master to
read a timekeeping register). Collision-detection circuit-
ry ensures that this does not happen coincident with a
seconds counter update to ensure accurate time data
is being read. This avoids time data changes during a
read operation. The clock counters continue to count
and keep accurate time during the read operation.
If single reads are to be used to read each of the time-
keeping registers individually, then it is necessary to do
some error checking on the receiving end. The poten-
tial for error is the case when the seconds counter
increments before all the other registers are read out.
For example, suppose a carry of 13:59:59 to 14:00:00
occurs during single read operations of the timekeep-
ing registers. Then, the net data could become
14:59:59, which is erroneous real-time data. To prevent
this with single-read operations, read the seconds reg-
ister first (initial seconds) and store this value for future
comparison. When the remaining timekeeping registers
have been read out, read the seconds register again
(final seconds). If the initial seconds value is 59, check
that the final seconds value is still 59; if not, repeat the
entire single-read process for the timekeeping regis-
ters. A comparison of the initial seconds value with the
final seconds value can indicate if there was a bus
delay problem in reading the timekeeping data (differ-
ence should always be 1s or less). Using a 100kHz bus
speed, sequential single reads would take under 2.5ms
to read all seven of the timekeeping registers, plus a
second read of the seconds register.
Reading from the Timekeeping Registers
Address/Command Byte
27