AD7248AAQ AD [Analog Devices], AD7248AAQ Datasheet - Page 10

• Manufacturer Part Number: AD7248AAQ
• Description: LC2MOS 12-Bit DACPORTs
• Manufacturer: AD [Analog Devices]

AD7245A/AD7248A
the simultaneous updating of multiple AD7248A outputs. How-
ever, in systems where the asynchronous LDAC can occur dur-
ing a write cycle (or vice versa) care must be taken to ensure
that incorrect data is not latched through to the output. In other
words, if LDAC goes low while WR and either CS input are low
(or WR and either CS go low while LDAC is low), then the
LDAC signal must stay low for t
high to ensure correct data is latched through to the output.
The write cycle timing diagram for the AD7248A is shown in
Figure 7.
An alternate scheme for writing data to the AD7248A is to tie
the CSMSB and LDAC inputs together. In this case exercising
CSLSB and WR latches the lower 8 bits into the input latch.
The second write, which exercises CSMSB, WR and LDAC
loads the upper 4-bit nibble to the input latch and at the same
time transfers the 12-bit data to the DAC latch. This automatic
transfer mode updates the output of the AD7248A in two write
operations. This scheme works equally well for CSLSB and
LDAC tied together provided the upper 4-bit nibble is loaded to
the input latch followed by a write to the lower 8 bits of the in-
put latch.
CSLSB CSMSB WR LDAC Function
L
L
g
H
H
H
H
H
H
H
H = High State L = Low State
APPLYING THE AD7245A/AD7248A
The internal scaling resistors provided on the AD7245A/
AD7248A allow several output voltage ranges. The part can
produce unipolar output ranges of 0 V to +5 V or 0 V to +10 V
and a bipolar output range of –5 V to +5 V. Connections for the
various ranges are outlined below.
Figure 7. AD7248A Write Cycle Timing Diagram
H
H
H
L
L
g
H
H
L
H
Table II. AD7248A Truth Table
L
g
L
L
g
L
H
H
L
H
H
H
H
H
H
H
L
g
L
H
I.oad LS Byte into Input Latch
Latches LS Byte into Input Latch
Latches LS Byte into Input Latch
Loads MS Nibble into Input Latch
Latches MS Nibble into Input Latch
Latches MS Nibble into Input Latch
Loads Input Latch into DAC Latch
Latches Input Latch into DAC Latch
Loads MS Nibble into Input Latch and
Loads Input Latch into DAC Latch
No Data Transfer Operation
7
or longer after WR returns
–10–
UNIPOLAR (0 V TO +10 V) CONFIGURATION
The first of the configurations provides an output voltage range
of 0 V to +10 V. This is achieved by connecting the bipolar off-
set resistor, R
this configuration the AD7245A/AD7248A can be operated
single supply (V
is required, a V
shows the connection diagram for unipolar operation while the
table for output voltage versus the digital code in the DAC latch
is shown in Table III.
DAC Latch Contents
MSB
1 1 1 1
1 0 0 0
1 0 0 0
0 1 1 1
0 0 0 0
0 0 0 0
NOTE: 1 LSB = 2
UNIPOLAR (0 V TO +5 V) CONFIGURATION
The 0 V to +5 V output voltage range is achieved by tying R
R
AD7248A can be operated single supply (V
supply. The table for output voltage versus digital code is as in
Table III, with 2 • V
range
FB
and V
Table III. Unipolar Code Table (0 V to +10 V Range)
Figure 8. Unipolar (0 to +10 V) Configuration
1 LSB = V
OUT
1 1 1 1
0 0 0 0
0 0 0 0
1 1 1 1
0 0 0 0
0 0 0 0
OFS
together. For this output range the AD7245A/
SS
SS
, to AGND and connecting R
of –12 V to –15 V should be applied. Figure 8
= 0 V = AGND). If dual supply performance
REF
REF
LSB
1 1 1 1
0 0 0 1
0 0 0 0
1 1 1 1
0 0 0 1
0 0 0 0
(2
V
replaced by V
REF
–12
) = V
(2
–12
) = V
REF
Analog Output, V
+2 V
+2 V
+2 V
+2 V
+2 V
REF
REF
REF
REF
REF
REF
REF
. Note that for this
4096
0 V
1
SS
2048
1
= 0 V) or dual
FB
4095
4096
2049
4096
2048
4096
2047
4096
4096
.
1
to V
OUT
OUT
REV. A
. In
V
REF
OFS
,