AD7248AAQ AD [Analog Devices], AD7248AAQ Datasheet - Page 13

• Manufacturer Part Number: AD7248AAQ
• Description: LC2MOS 12-Bit DACPORTs
• Manufacturer: AD [Analog Devices]

REV. A
In a multiple DAC system the double buffering of the AD7245A
allows the user to simultaneously update all DACs. In Figure
13, a 12-bit word is loaded to the input latches of each of the
DACs in sequence. Then, with one instruction to the appropri-
ate address, CS4 (i.e., LDAC) is brought LOW, updating all the
DACs simultaneously.
AD7245A—MC68000 INTERFACE
Interfacing between the MC68000 and the AD7245A is accom-
plished using the circuit of Figure 14. Once again the AD7245A
is used in the single buffered mode. A software routine for load-
ing data to the AD7245A is given in Table VI. In this example
the AD7245A is located at address E000, and the 12-bit word is
written to the DAC in one MOVE instruction.
Figure 13. AD7245A to 8086 Multiple DAC Interface
Figure 14. AD7245A to 68000 Interface
–13–
01000
MICROPROCESSOR INTERFACE—AD7248A
Figure 15 shows the connection diagram for interfacing the
AD7248A to both the 8085A and 8088 microprocessors. This
scheme is also suited to the Z80 microprocessor, but the Z80
address/data bus does not have to be demultiplexed. Data to be
loaded to the AD7248A is right justified. The AD7248A is
memory mapped with a separate memory address for the input
latch high byte, the input latch low byte and the DAC latch.
Data is first written to the AD7248A input latch in two write
operations. Either the high byte or the low byte data can be
written first to the AD7248A input latch. A write to the
AD7248A DAC latch address transfers the input latch data to
the DAC latch and updates the output voltage. Alternatively,
the LDAC input can be asynchronous or can be common to a
number of AD7248As for simultaneous updating of a number of
voltage channels.
A connection diagram for the interface between the AD7248A
and 68008 microprocessor is shown in Figure 16. Once again
the AD7248A acts as a memory mapped device and data is right
justified. In this case the AD7248A is configured in the auto-
matic transfer mode which means that the high byte of the input
latch has the same address as the DAC latch. Data is written to
the AD7248A by first writing data to the AD7248A low byte.
Writing data to the high byte of the input latch also transfers the
input latch contents to the DAC latch and updates the output.
Table Vl. Sample Routine for Loading AD7245A from 68000
Figure 15. AD7248A to 8085A/8088 Interface
MOVE.W
MOVE.W
MOVE.B
TRAP
#X,D0
D0,$E000
#228,D7
#14
AD7245A/AD7248A
The desired DAC data, X,
is loaded into Data Re-
gister 0. X may be any
value between 0 and 4094
(decimal) or 0 and OFFF
(hexadecimal).
The Data X is transferred
between D0 and the
DAC Latch.
Control is returned to the
System Monitor Program
using these two
instructions.