AD7248AAQ AD [Analog Devices], AD7248AAQ Datasheet - Page 2

• Manufacturer Part Number: AD7248AAQ
• Description: LC2MOS 12-Bit DACPORTs
• Manufacturer: AD [Analog Devices]

AGND = DGND = O V, R
Parameter
STATIC PERFORMANCE
REFERENCE OUTPUT
DIGITAL INPUTS
ANALOG OUTPUTS
AC CHARACTERISTICS
POWER REQUIREMENTS
NOTES
1
2
3
4
5
6
7
8
9
10
Specifications subject to change without notice.
AD7245A/AD7248A–SPECIFICATIONS
Power supply tolerance is 10% for A Version and 5% for B and T Versions.
Temperature ranges are as follows: A/B Versions; –40 C to +85 C; T Version; –55 C to +125 C.
See Terminology.
With appropriate power supply tolerances.
FSR means Full-Scale Range and is 5 V for the 0 V to +5 V output range and 10 V for both the 0 V to +10 V and
This error is calculated with respect to the reference voltage and is measured after the offset error has been allowed for.
This error is calculated with respect to an ideal 4.9988 V on rhe 0 V to +5 V and 5 V ranges; it is calculated with respect to an ideal 9.9976 V on the
Full-Scale TC = FS/ T, where FS is the full-scale change from T
Sample tested at +25 C to ensure compliance.
0 V to +10 V range. It includes the effects of internal voltage reference, gain and offset errors.
0 V to +10 V output range is available only when V
Resolution
Relative Accuracy @ +25 C
T
T
Differential Nonlinearity
Unipolar Offset Error @ +25 C
Bipolar Zero Error @ +25 C
DAC Gain Error
Full-Scale Output Voltage Error
Full-Scale Temperature Coefficient
REF OUT @ +25 C
Reference Temperature Coefficient
Reference Load Change
Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance
Output Range Resistors
Output Voltage Ranges
Output Voltage Ranges
DC Output Impedance
Voltage Output Settling Time
Output Voltage Slew Rate
Digital Feedthrough
Digital-to-Analog Glitch Impulse
V
V
I
T
I
DD
SS
Full Scale/ V
Full Scale/ V
REF OUT/ V
MIN
MIN
DD
SS
MlN
T
T
( REF OUT vs. I)
Positive Full-Scale Change
Negative Full-Scale Change
(Dual Supplies)
MIN
MIN
@ +25 C
to T
to T
to T
to T
to T
MAX
MAX
MAX
MAX
MAX
DD
SS
DD
IN
3, 6
9
3
L
INL
INH
10
10
= 2 k , C
3
9
3
3
3
7
@ +25 C
L
8
= 1OO pF. All specifications T
A
Version Version
12
4.99/5.01 4.99/5.01
2
–1
2.4
0.8
8
15/30
+5, +10
+5, +10, +5, +10,
0.5
7
7
2
10
30
+10.8/
+16.5
–10.8/
–16.5
9
10
3
3/4
1
1
3
5
3
5
2
0.2
0.06
0.01
30
25
10
5
2
DD
+14.25 V.
B
12
2
–1
2.4
0.8
8
15/30
+5, +10
0.5
7
7
2
10
30
+11.4/
+15.75
–11.4/
–15.75
9
10
3
1/2
3/4
1/2
1
3
5
2
4
2
0.2
0.06
0.01
30
25
10
5
2
A
= +25 C to T
T
Version Units
12
4.99/5.01 V min/V max
2
–1
2.4
0.8
8
15/30
+5, +10
+5, +10,
0.5
10
10
1.5
10
30
+11.4/
+15.75
–11.4/
–15.75
9
12
5
MIN
2
1/2
3/4
1
3
5
2
4
2
0.2
0.06
0.01
40
35
10
5
to T
–2–
MAX
MIN
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
% of FSR max
% of FSR/V max
% of FSR/V max
ppm of FSR/ C max V
mV/V max
ppm/ C typ
mV max
V min
V max
pF max
k min/k max
V
V
V/ s min
nV-s typ
nV-s typ
V min/
V max
V min/
V max
mA max
mA max
mA max
A max
s max
s max
unless otherwise noted.)
typ
or T
MAX
(V
DD
.
= +12 V to +15 V,
For Specified Performance Unless Otherwise Stated
For Specified Performance Unless Otherwise Stated
Test Conditions/Comments
V
Guaranteed Monotonic
V
Typical Tempco is 3 ppm of FSR
R
Typical Tempco is 3 ppm of FSR
V
V
V
V
V
Referenee Load Current Change (0–100 A)
V
V
V
Settling Time to Within 1/2 LSB of Final Value
DAC Latch All 0s to All 1s
DAC Latch All 1s to All 0s; V
Output Unloaded; Typically 5 mA
Output Unloaded
Output Unloaded; Typically 2 mA
DD
SS
OFS
DD
DD
SS
DD
DD
DD
IN
SS
SS
= 0 V or –12 V to –15 V
= –12 V to –15 V
= 0 V to V
= 0 V; Pin Strappable
= –12 V to –15 V;
= 15 V
= +15 V
= +12 V to +15 V
= +15 V
= +15 V
= +12 V to +15 V
connected to REF OUT; V
5 V output ranges.
1
V
SS
= O V or –12 V to –15 V,
5%
DD
4
4
4
4
Pin Strappable
4
SS
SS
= –12 V to –15 V
= –12 V to –15 V
5
5
/ C.
/ C.
1
REV. A
4
4