ADV7181 AD [Analog Devices], ADV7181 Datasheet - Page 66

• Manufacturer Part Number: ADV7181
• Description: Multiformat SDTV Video Decoder
• Manufacturer: AD [Analog Devices]

ADV7181B
I
The following registers are located in Register Access Page 2.
Table 82. Interrupt Register Map Details
Register
Name
Interrupt
Config 0
Reserved
Interrupt
Status 1
Interrupt
Clear 1
Interrupt
Maskb 1
Reserved
Interrupt
Status 2
Interrupt
Clear 2
Interrupt
Maskb 2
Raw Status 3
Interrupt
Status 3
Interrupt
Clear 3
Interrupt
Maskb 3
4
Table 83. Interrupt Register Map Details
Subaddress
0x40
2
To access the Interrupt Register Map, the Register Access page [1:0] bits in Register Address 0x0E must be programmed to 01b.
C REGISTER MAP DETAILS
Register
Interrupt
Config 1
Register
Access
Page 2
Reset
Value
0001 x000
x000 0000
x000 0000
0xxx 0000
0xxx 0000
xx00 0000
xx00 0000
Bit Description
INTRQ_OP_SEL[1:0].
Interrupt Drive Level Select
MPU_STIM_INTRQ[1:0].
Manual Interrupt Set Mode
Reserved
MV_INTRQ_SEL[1:0].
Macrovision Interrupt Select
INTRQ_DUR_SEL[1:0].
Interrupt duration Select
rw
rw
r
w
rw
r
w
rw
r
r
w
rw
Subaddress
Dec
64
65
66
67
68
69
70
71
72
73
74
75
76
4
Hex
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
Bit 7
INTRQ_
DUR_SEL.1
MPU_
STIM_
INTRQ_Q
MPU_
STIM_INT
RQ_CLR
MPU_
STIM_INT
RQ_MSKB
7
0
0
1
1
Rev. 0 | Page 66 of 96
Bit 6
INTRQ_
DUR_SEL.0
MV_PS_
CS_Q
MV_PS_
CS_CLR
MV_PS_
CS_MSKB
6
0
1
0
1
0
0
1
1
5
4
0
1
0
1
Bit
Bit 5
MV_INTRQ
_SEL.1
SD_FR_
CHNG_Q
SD_FR_
CHNG_CLR
SD_FR_
CHNG_
MSKB
PAL_SW_
LK_
CHNG_Q
PAL_SW_
LK_CHNG
_CLR
PAL_SW_
LK_CHNG
_MSKB
3
x
2
0
1
1
0
0
1
1
MV_INTRQ
_SEL.0
SCM_
LOCK
SCM_
LOCK_
CHNG_Q
SCM_
LOCK_
CHNG_CLR
SCM_
LOCK_CH
NG_MSKB
Bit 4
0
0
1
0
1
Comments
Open drain
Drive low when active
Drive high when active
Reserved
Manual interrupt mode disabled
Manual interrupt mode enabled
Not used
Reserved
Pseudo sync only
Color stripe only
Pseudo sync or color stripe
3 Xtal periods
15 Xtal periods
63 Xtal periods
Active until cleared
WSS_
CHNGD_Q
WSS_
CHNGD_
CLR
WSS_CHN
GD_MSKB
SD_AD_
CHNG_Q
SD_AD_
CHNG_
CLR
SD_AD_
CHNG_
MSKB
Bit 3
Bit 2
MPU_
STIM_INTRQ
CGMS_
CHNGD_Q
CGMS_
CHNGD_
CLR
CGMS_
CHNGD_
MSKB
SD_H_
LOCK
SD_H_
LOCK_
CHNG_Q
SD_H_
LOCK_
CHNG_CLR
SD_H_
LOCK_CH
NG_MSKB
Bit 1
INTRQ_
OP_SEL.1
SD_
UNLOCK_Q
SD_UNLO
CK_CLR
SD_
UNLOCK_
MSKB
GEMD_Q
GEMD_
CLR
GEMD_
MSKB
SD_V_
LOCK
SD_V_
LOCK_
CHNG_Q
SD_V_LO
CK_CHNG
_CLR
SD_V_
LOCK_CH
NG_MSKB
Notes
SD_OP_
CHNG_CLR
Bit 0
INTRQ_
OP_SEL.0
SD_LOCK_
Q
SD_LOCK
_CLR
SD_LOCK
_MSKB
CCAPD_Q
CCAPD_
CLR
CCAPD_
MSKB
SD_OP_
50HZ
SD_OP_
CHNG_Q
SD_OP_
CHNG_
MSKB