PCA9698DGG NXP [NXP Semiconductors], PCA9698DGG Datasheet - Page 7

• Manufacturer Part Number: PCA9698DGG
• Description: 40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
7. Functional description
PCA9698
Product data sheet
7.1 Device address
Table 2.
[1]
Refer to
Following a START condition the bus master must send the address of the slave it is
accessing and the operation it wants to perform (read or write). The address of the
PCA9698 is shown in
64 slave addresses. To conserve power, no internal pull-up resistors are incorporated on
AD2, AD1 and AD0. Address values depending on AD2, AD1 and AD0 can be found in
Table 12 “PCA9698 address
The last bit of the first byte defines the operation to be performed. When set to logic 1 a
read is selected while a logic 0 selects a write operation.
Symbol
AD2
OE
INT/SMBALERT
RESET
Fig 5.
HVQFN56 package die supply ground is connected to both V
must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and
board level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board and for proper heat conduction through the board, thermal vias need to be
incorporated in the printed-circuit board in the thermal pad region.
Figure 1 “Block diagram of
PCA9698 device address
Pin description
All information provided in this document is subject to legal disclaimers.
Pin
TSSOP56
29
30
55
56
Figure
40-bit Fm+ I
Rev. 3 — 3 August 2010
…continued
map”.
5. Slave address pins AD2, AD1 and AD0 choose 1 of
A6
HVQFN56
22
23
48
49
A5
2
PCA9698”.
C-bus advanced I/O port with RESET, OE and INT
programmable
slave address
A4
A3
A2
Type
input
input
output
input
A1
SS
002aab937
A0
pins and exposed center pad. V
R/W
Description
address input 2
active LOW output enable
active LOW interrupt output/
active LOW SMBus alert
output
active LOW reset input
PCA9698
© NXP B.V. 2010. All rights reserved.
SS
pins
7 of 48