DAC1408D650HN NXP [NXP Semiconductors], DAC1408D650HN Datasheet - Page 18

• Manufacturer Part Number: DAC1408D650HN
• Description: Dual 14-bit DAC; up to 650 Msps; 2?, 4? or 8? interpolating with JESD204A interface
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
DAC1408D650
Product data sheet
The MDS signal generated by the master DAC must reach all slaves within one DAC
output clock period. This induces PCB layout constraints for the MDS signal and also for
the clock distribution. Because trace lengths differ, the clock edges reach each of the
DACs at different times.
The worst case clock skew is given by
sum of the trace delay and the clock skew at the output of the clock generator.
The maximum allowable trace delay for the MDS signal is given by
Fig 9.
Clock skew case 1: Master is farthest
slave 1 clock
slave 2 clock
master clock
All information provided in this document is subject to legal disclaimers.
ref clock
Rev. 4 — 26 November 2010
PH03
PH02
t
PH01
2, 4 or 8 interpolating DAC with JESD204A
1
TDAC
=
PH01 PH03
–
DAC1408D650
, where PH0x represents the
t
001aal072
=
© NXP B.V. 2010. All rights reserved.
TDAC t
–
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1
.