DAC1408D650HN NXP [NXP Semiconductors], DAC1408D650HN Datasheet - Page 21

• Manufacturer Part Number: DAC1408D650HN
• Description: Dual 14-bit DAC; up to 650 Msps; 2?, 4? or 8? interpolating with JESD204A interface
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
DAC1408D650
Product data sheet
10.2.6 Frame assembly
DAC1408D650 supports only /F/ = 1, which means that every frame clock period carries
one byte per lane. Frame assembly combines the octet of lane_0 with the six MSB bits of
lane_1 and reassembles the original 14-bit sample. The same is done for lane_2 and
lane_3. Tail bits are dropped.
The frame assembler also handles previously triggered errors.
If scrambling is enabled:
If scrambling is disabled:
If a nit_err (not-in-table error) or kout_unexp (unexpected control character) occurs in
lane_0 and/or lane_1, the previous 14-bit sample is repeated twice for I (lane_0,
lane_1). The same is done for Q (lane_2, lane_3).
If a nit_err (not-in-table error) or kout_unexp (unexpected control character) occurs in
lane_0 and/or lane_1, the previous 14-bit sample is repeated once for I (lane_0,
lane_1). The same is done for Q (lane_2, lane_3).
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 26 November 2010
2, 4 or 8 interpolating DAC with JESD204A
DAC1408D650
© NXP B.V. 2010. All rights reserved.
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