ISL70001SRHF INTERSIL [Intersil Corporation], ISL70001SRHF Datasheet - Page 9

• Manufacturer Part Number: ISL70001SRHF
• Description: Rad Hard and SEE Hard 6A Synchronous Buck Regulator
• Manufacturer: INTERSIL [Intersil Corporation]

Functional Description
The ISL70001SEH is a monolithic, fixed frequency, current-mode
synchronous buck regulator with user configurable power blocks.
Two ISL70001SEH devices can be used to provide a total DC/DC
solution for FPGAs, CPLDs, DSPs and CPUs.
The ISL70001SEH utilizes peak current-mode control with
integrated compensation and switches at a fixed frequency of
1MHz. Two ISL70001SEH devices can be synchronized 180°
out-of-phase to reduce input RMS ripple current. These attributes
reduce the number and size of external components required,
while providing excellent output transient response. The
internal synchronous power switches are optimized for high
efficiency and good thermal performance.
The chip features a comparator type enable input that provides
flexibility. It can be used for simple digital on/off control or,
alternately, can provide undervoltage lockout capability by
using two external resistors to precisely sense the level of an
external supply voltage. A power-good signal indicates when the
output voltage is within ±11% typical of the nominal output
voltage.
Regulator start-up is controlled by an analog soft-start circuit,
which can be adjusted from approximately 2ms to 200ms by
using an external capacitor.
The ISL70001SEH incorporates fault protection for the
regulator. The protection circuits include input undervoltage,
output undervoltage, and output overcurrent.
Power Blocks
The power output stage of the regulator consists of six 1A
capable power blocks that are paralleled to provide full 6A
output current capability. The block diagram in Figure 5 shows a
top level view of the individual power blocks.
Each power block has a power supply input pin, PVINx, a phase
output pin, LXx, and a power supply ground pin, PGNDx. All PVINx
pins must be connected to a common power supply rail and all
PGNDx pins must be connected to a common ground. LXx pins
should be connected to the output inductor based on the
required load current, but must include the LX4 pin. For example,
if 3A of output current is needed, any three LXx pins can be
connected to the inductor as long as one of them is the LX4 pin.
The unused LXx pins should be left unconnected. Connecting all
six LXx pins to the output inductor provides a maximum 6A of
PGND1
PGND2
PGND3
PVIN1
PVIN2
PVIN3
LX1
LX2
LX3
POWER BLOCK 1
POWER BLOCK 2
POWER BLOCK 3
FIGURE 5. POWER BLOCK DIAGRAM
9
POWER BLOCK 6
POWER BLOCK 5
POWER BLOCK 4
ISL70001SEH
PVIN5
LX5
PVIN6
LX6
PGND6
PGND5
PVIN4
LX4
PGND4
output current. See the “Typical Application Schematic” on
page 5 for pin connection guidance.
A scaled pilot device associated with each power block provides
current feedback. Power block 4 contains the master pilot device
and this is why it must be connected to the output inductor.
Main Control Loop
During normal operation, the internal top power switch is turned
on at the beginning of each clock cycle. Current in the output
inductor ramps up until the current comparator trips and turns
off the top power MOSFET. The bottom power MOSFET turns on
and the inductor current ramps down for the rest of the cycle.
The current comparator compares the output current at the
ripple current peak to a current pilot. The error amplifier monitors
V
output voltage of the error amplifier drives a proportional current
to the pilot. If V
increased and the trip off current level of the output is increased.
The increased output current raises V
with the reference voltage.
Output Voltage Selection
The output voltage of the ISL70001SEH can be adjusted using an
external resistor divider as shown in Figure 6.
R
shunted by a 4.7nF ceramic capacitor, C
improve loop stability margins. The REF pin should be bypassed
to AGND with a 220nF ceramic capacitor to mitigate SEE. It
should be noted that no current (sourcing or sinking) is available
from the REF pin. R
designer can configure the output voltage from 0.8V to 85% of
the input voltage.
Switching Frequency/Synchronization
The ISL70001SEH features an internal oscillator running at a
fixed frequency of 1MHz ±15% over recommended operating
conditions. The regulator can be configured to run from the
internal oscillator or can be synchronized to another
ISL70001SEH or an SEE hardened external clock with a
frequency range of 1MHz ±20%.
R
OUT
T
B
should be selected as 1kΩ to mitigate SEE. R
=
and compares it with an internal reference voltage. The
R
T
V
C
R
C
REF
⋅
REF
T
C
------------------------------- -
V
= 1k
= 4.7nF
OUT
AMPLIFIER
= 0.6V
= 220nF
FIGURE 6. OUTPUT VOLTAGE SELECTION
V
ERROR
REF
–
OUT
+
-
V
REF
V
is low, the current level of the pilot is
REF
B
can be determined from Equation 3. The
FB
REF
LXx
L
OUT
OUT
C
REF
C
, to mitigate SEE and to
until it is in agreement
C
OUT
T
R
R
November 30, 2011
should be
T
B
V
OUT
C
C
FN7956.0
(EQ. 3)